diff options
| -rw-r--r-- | llvm/lib/Target/PowerPC/PPCFrameLowering.cpp | 11 | ||||
| -rw-r--r-- | llvm/test/CodeGen/PowerPC/no-dup-spill-fp.ll | 26 |
2 files changed, 37 insertions, 0 deletions
diff --git a/llvm/lib/Target/PowerPC/PPCFrameLowering.cpp b/llvm/lib/Target/PowerPC/PPCFrameLowering.cpp index 1d8aaac46d3..c59c619e0bc 100644 --- a/llvm/lib/Target/PowerPC/PPCFrameLowering.cpp +++ b/llvm/lib/Target/PowerPC/PPCFrameLowering.cpp @@ -1419,6 +1419,17 @@ void PPCFrameLowering::determineCalleeSaves(MachineFunction &MF, FI->setPICBasePointerSaveIndex(PBPSI); } + // Make sure we don't explicitly spill r31, because, for example, we have + // some inline asm which explicity clobbers it, when we otherwise have a + // frame pointer and are using r31's spill slot for the prologue/epilogue + // code. Same goes for the base pointer and the PIC base register. + if (needsFP(MF)) + SavedRegs.reset(isPPC64 ? PPC::X31 : PPC::R31); + if (RegInfo->hasBasePointer(MF)) + SavedRegs.reset(RegInfo->getBaseRegister(MF)); + if (FI->usesPICBase()) + SavedRegs.reset(PPC::R30); + // Reserve stack space to move the linkage area to in case of a tail call. int TCSPDelta = 0; if (MF.getTarget().Options.GuaranteedTailCallOpt && diff --git a/llvm/test/CodeGen/PowerPC/no-dup-spill-fp.ll b/llvm/test/CodeGen/PowerPC/no-dup-spill-fp.ll new file mode 100644 index 00000000000..95e069b5455 --- /dev/null +++ b/llvm/test/CodeGen/PowerPC/no-dup-spill-fp.ll @@ -0,0 +1,26 @@ +; RUN: llc < %s | FileCheck %s +target datalayout = "E-m:e-i64:64-n32:64" +target triple = "powerpc64" + +; Function Attrs: nounwind +define void @test() #0 { +entry: + call void @func() + call void asm sideeffect "nop", "~{r31}"() #1, !srcloc !0 + ret void + +; CHECK-LABEL: @test +; CHECK: std 31, -8(1) +; CHECK: stdu 1, -{{[0-9]+}}(1) +; CHECK-NOT: std 31, +; CHECK: bl func +; CHECK: ld 31, -8(1) +; CHECK: blr +} + +declare void @func() + +attributes #0 = { nounwind "no-frame-pointer-elim"="true" "no-frame-pointer-elim-non-leaf" "target-cpu"="ppc64" } +attributes #1 = { nounwind } + +!0 = !{i32 57} |
