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authorHal Finkel <hfinkel@anl.gov>2016-08-31 00:52:03 +0000
committerHal Finkel <hfinkel@anl.gov>2016-08-31 00:52:03 +0000
commit97a189c7169cfaf927c32b3870675ae161970e09 (patch)
tree707bff6ac017b683897648b167de71564726b7aa
parent3766d106c811117325e6a7b6054cfa351c61aa5e (diff)
downloadbcm5719-llvm-97a189c7169cfaf927c32b3870675ae161970e09.tar.gz
bcm5719-llvm-97a189c7169cfaf927c32b3870675ae161970e09.zip
[PowerPC] Don't spill the frame pointer twice
When a function contains something, such as inline asm, which explicitly clobbers the register used as the frame pointer, don't spill it twice. If we need a frame pointer, it will be saved/restored in the prologue/epilogue code. Explicitly spilling it again will reuse the same spill slot used by the prologue/epilogue code, thus clobbering the saved value. The same applies to the base-pointer or PIC-base register. Partially fixes PR26856. Thanks to Ulrich for his analysis and the small inline-asm reproducer. llvm-svn: 280188
-rw-r--r--llvm/lib/Target/PowerPC/PPCFrameLowering.cpp11
-rw-r--r--llvm/test/CodeGen/PowerPC/no-dup-spill-fp.ll26
2 files changed, 37 insertions, 0 deletions
diff --git a/llvm/lib/Target/PowerPC/PPCFrameLowering.cpp b/llvm/lib/Target/PowerPC/PPCFrameLowering.cpp
index 1d8aaac46d3..c59c619e0bc 100644
--- a/llvm/lib/Target/PowerPC/PPCFrameLowering.cpp
+++ b/llvm/lib/Target/PowerPC/PPCFrameLowering.cpp
@@ -1419,6 +1419,17 @@ void PPCFrameLowering::determineCalleeSaves(MachineFunction &MF,
FI->setPICBasePointerSaveIndex(PBPSI);
}
+ // Make sure we don't explicitly spill r31, because, for example, we have
+ // some inline asm which explicity clobbers it, when we otherwise have a
+ // frame pointer and are using r31's spill slot for the prologue/epilogue
+ // code. Same goes for the base pointer and the PIC base register.
+ if (needsFP(MF))
+ SavedRegs.reset(isPPC64 ? PPC::X31 : PPC::R31);
+ if (RegInfo->hasBasePointer(MF))
+ SavedRegs.reset(RegInfo->getBaseRegister(MF));
+ if (FI->usesPICBase())
+ SavedRegs.reset(PPC::R30);
+
// Reserve stack space to move the linkage area to in case of a tail call.
int TCSPDelta = 0;
if (MF.getTarget().Options.GuaranteedTailCallOpt &&
diff --git a/llvm/test/CodeGen/PowerPC/no-dup-spill-fp.ll b/llvm/test/CodeGen/PowerPC/no-dup-spill-fp.ll
new file mode 100644
index 00000000000..95e069b5455
--- /dev/null
+++ b/llvm/test/CodeGen/PowerPC/no-dup-spill-fp.ll
@@ -0,0 +1,26 @@
+; RUN: llc < %s | FileCheck %s
+target datalayout = "E-m:e-i64:64-n32:64"
+target triple = "powerpc64"
+
+; Function Attrs: nounwind
+define void @test() #0 {
+entry:
+ call void @func()
+ call void asm sideeffect "nop", "~{r31}"() #1, !srcloc !0
+ ret void
+
+; CHECK-LABEL: @test
+; CHECK: std 31, -8(1)
+; CHECK: stdu 1, -{{[0-9]+}}(1)
+; CHECK-NOT: std 31,
+; CHECK: bl func
+; CHECK: ld 31, -8(1)
+; CHECK: blr
+}
+
+declare void @func()
+
+attributes #0 = { nounwind "no-frame-pointer-elim"="true" "no-frame-pointer-elim-non-leaf" "target-cpu"="ppc64" }
+attributes #1 = { nounwind }
+
+!0 = !{i32 57}
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