diff options
| -rw-r--r-- | llvm/include/llvm/Support/TargetOpcodes.def | 6 | ||||
| -rw-r--r-- | llvm/include/llvm/Target/GenericOpcodes.td | 15 | ||||
| -rw-r--r-- | llvm/lib/CodeGen/GlobalISel/IRTranslator.cpp | 10 | ||||
| -rw-r--r-- | llvm/test/CodeGen/AArch64/GlobalISel/arm64-irtranslator.ll | 20 |
4 files changed, 51 insertions, 0 deletions
diff --git a/llvm/include/llvm/Support/TargetOpcodes.def b/llvm/include/llvm/Support/TargetOpcodes.def index 9143e5b9dd9..dfd15ac22d9 100644 --- a/llvm/include/llvm/Support/TargetOpcodes.def +++ b/llvm/include/llvm/Support/TargetOpcodes.def @@ -268,6 +268,12 @@ HANDLE_TARGET_OPCODE(G_INTTOPTR) /// COPY is the relevant instruction. HANDLE_TARGET_OPCODE(G_BITCAST) +/// INTRINSIC trunc intrinsic. +HANDLE_TARGET_OPCODE(G_INTRINSIC_TRUNC) + +/// INTRINSIC round intrinsic. +HANDLE_TARGET_OPCODE(G_INTRINSIC_ROUND) + /// Generic load (including anyext load) HANDLE_TARGET_OPCODE(G_LOAD) diff --git a/llvm/include/llvm/Target/GenericOpcodes.td b/llvm/include/llvm/Target/GenericOpcodes.td index 90c121dfe3a..2a2bef2fb38 100644 --- a/llvm/include/llvm/Target/GenericOpcodes.td +++ b/llvm/include/llvm/Target/GenericOpcodes.td @@ -513,6 +513,21 @@ def G_FLOG2 : GenericInstruction { } //------------------------------------------------------------------------------ +// Opcodes for LLVM Intrinsics +//------------------------------------------------------------------------------ +def G_INTRINSIC_TRUNC : GenericInstruction { + let OutOperandList = (outs type0:$dst); + let InOperandList = (ins type0:$src1); + let hasSideEffects = 0; +} + +def G_INTRINSIC_ROUND : GenericInstruction { + let OutOperandList = (outs type0:$dst); + let InOperandList = (ins type0:$src1); + let hasSideEffects = 0; +} + +//------------------------------------------------------------------------------ // Memory ops //------------------------------------------------------------------------------ diff --git a/llvm/lib/CodeGen/GlobalISel/IRTranslator.cpp b/llvm/lib/CodeGen/GlobalISel/IRTranslator.cpp index 74f51cc7292..3fda5cb9007 100644 --- a/llvm/lib/CodeGen/GlobalISel/IRTranslator.cpp +++ b/llvm/lib/CodeGen/GlobalISel/IRTranslator.cpp @@ -850,6 +850,16 @@ bool IRTranslator::translateKnownIntrinsic(const CallInst &CI, Intrinsic::ID ID, .addDef(getOrCreateVReg(CI)) .addUse(getOrCreateVReg(*CI.getArgOperand(0))); return true; + case Intrinsic::trunc: + MIRBuilder.buildInstr(TargetOpcode::G_INTRINSIC_TRUNC) + .addDef(getOrCreateVReg(CI)) + .addUse(getOrCreateVReg(*CI.getArgOperand(0))); + return true; + case Intrinsic::round: + MIRBuilder.buildInstr(TargetOpcode::G_INTRINSIC_ROUND) + .addDef(getOrCreateVReg(CI)) + .addUse(getOrCreateVReg(*CI.getArgOperand(0))); + return true; case Intrinsic::fma: MIRBuilder.buildInstr(TargetOpcode::G_FMA) .addDef(getOrCreateVReg(CI)) diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/arm64-irtranslator.ll b/llvm/test/CodeGen/AArch64/GlobalISel/arm64-irtranslator.ll index 75615e9d6c1..cf30558d5d6 100644 --- a/llvm/test/CodeGen/AArch64/GlobalISel/arm64-irtranslator.ll +++ b/llvm/test/CodeGen/AArch64/GlobalISel/arm64-irtranslator.ll @@ -1408,6 +1408,26 @@ define float @test_fabs_intrin(float %a) { ret float %res } +declare float @llvm.trunc.f32(float) +define float @test_intrinsic_trunc(float %a) { +; CHECK-LABEL: name: test_intrinsic_trunc +; CHECK: [[A:%[0-9]+]]:_(s32) = COPY $s0 +; CHECK: [[RES:%[0-9]+]]:_(s32) = G_INTRINSIC_TRUNC [[A]] +; CHECK: $s0 = COPY [[RES]] + %res = call float @llvm.trunc.f32(float %a) + ret float %res +} + +declare float @llvm.round.f32(float) +define float @test_intrinsic_round(float %a) { +; CHECK-LABEL: name: test_intrinsic_round +; CHECK: [[A:%[0-9]+]]:_(s32) = COPY $s0 +; CHECK: [[RES:%[0-9]+]]:_(s32) = G_INTRINSIC_ROUND [[A]] +; CHECK: $s0 = COPY [[RES]] + %res = call float @llvm.round.f32(float %a) + ret float %res +} + declare i32 @llvm.ctlz.i32(i32, i1) define i32 @test_ctlz_intrinsic_zero_not_undef(i32 %a) { ; CHECK-LABEL: name: test_ctlz_intrinsic_zero_not_undef |
