diff options
| -rw-r--r-- | llvm/lib/Target/X86/X86ISelLowering.cpp | 12 |
1 files changed, 6 insertions, 6 deletions
diff --git a/llvm/lib/Target/X86/X86ISelLowering.cpp b/llvm/lib/Target/X86/X86ISelLowering.cpp index 5371d0a0a26..30c05a3efb0 100644 --- a/llvm/lib/Target/X86/X86ISelLowering.cpp +++ b/llvm/lib/Target/X86/X86ISelLowering.cpp @@ -28545,17 +28545,12 @@ bool X86TargetLowering::isVectorShiftByScalarCheap(Type *Ty) const { bool X86TargetLowering::isBinOp(unsigned Opcode) const { switch (Opcode) { + // These are non-commutative binops. // TODO: Add more X86ISD opcodes once we have test coverage. case X86ISD::ANDNP: - case X86ISD::PMULUDQ: case X86ISD::FMAX: case X86ISD::FMIN: - case X86ISD::FMAXC: - case X86ISD::FMINC: - case X86ISD::FAND: case X86ISD::FANDN: - case X86ISD::FOR: - case X86ISD::FXOR: return true; } @@ -28566,6 +28561,11 @@ bool X86TargetLowering::isCommutativeBinOp(unsigned Opcode) const { switch (Opcode) { // TODO: Add more X86ISD opcodes once we have test coverage. case X86ISD::PMULUDQ: + case X86ISD::FMAXC: + case X86ISD::FMINC: + case X86ISD::FAND: + case X86ISD::FOR: + case X86ISD::FXOR: return true; } |
