diff options
| -rw-r--r-- | llvm/lib/Target/PowerPC/PPCISelLowering.cpp | 1 | ||||
| -rw-r--r-- | llvm/test/CodeGen/PowerPC/f32-to-i64.ll | 23 |
2 files changed, 24 insertions, 0 deletions
diff --git a/llvm/lib/Target/PowerPC/PPCISelLowering.cpp b/llvm/lib/Target/PowerPC/PPCISelLowering.cpp index 7e2e9b3d808..2df4c4899e2 100644 --- a/llvm/lib/Target/PowerPC/PPCISelLowering.cpp +++ b/llvm/lib/Target/PowerPC/PPCISelLowering.cpp @@ -7702,6 +7702,7 @@ void PPCTargetLowering::ReplaceNodeResults(SDNode *N, return; } case ISD::FP_TO_SINT: + case ISD::FP_TO_UINT: // LowerFP_TO_INT() can only handle f32 and f64. if (N->getOperand(0).getValueType() == MVT::ppcf128) return; diff --git a/llvm/test/CodeGen/PowerPC/f32-to-i64.ll b/llvm/test/CodeGen/PowerPC/f32-to-i64.ll new file mode 100644 index 00000000000..c1381880b75 --- /dev/null +++ b/llvm/test/CodeGen/PowerPC/f32-to-i64.ll @@ -0,0 +1,23 @@ +; RUN: llc < %s | FileCheck %s +target datalayout = "E-m:e-p:32:32-i64:64-n32" +target triple = "powerpc-unknown-unknown" + +; Function Attrs: nounwind +define i64 @testullf(float %arg) #0 { +entry: + %arg.addr = alloca float, align 4 + store float %arg, float* %arg.addr, align 4 + %0 = load float, float* %arg.addr, align 4 + %conv = fptoui float %0 to i64 + ret i64 %conv + +; CHECK-LABEL: @testullf +; CHECK: fctiduz [[REG1:[0-9]+]], 1 +; CHECK: stfd [[REG1]], [[OFF:[0-9]+]](1) +; CHECK-DAG: lwz 3, [[OFF]](1) +; CHECK-DAG: lwz 4, {{[0-9]+}}(1) +; CHECK: blr +} + +attributes #0 = { nounwind "target-cpu"="a2" } + |
