diff options
| -rw-r--r-- | llvm/lib/Target/AMDGPU/SIInstrInfo.td | 1 | ||||
| -rw-r--r-- | llvm/test/CodeGen/AMDGPU/ret.ll | 9 |
2 files changed, 5 insertions, 5 deletions
diff --git a/llvm/lib/Target/AMDGPU/SIInstrInfo.td b/llvm/lib/Target/AMDGPU/SIInstrInfo.td index fbdfc879770..862a32857c0 100644 --- a/llvm/lib/Target/AMDGPU/SIInstrInfo.td +++ b/llvm/lib/Target/AMDGPU/SIInstrInfo.td @@ -796,6 +796,7 @@ class EXPCommon : InstSI< let EXP_CNT = 1; let Uses = [EXEC]; + let SchedRW = [WriteExport]; } multiclass EXP_m { diff --git a/llvm/test/CodeGen/AMDGPU/ret.ll b/llvm/test/CodeGen/AMDGPU/ret.ll index 67824976609..915c4383ff4 100644 --- a/llvm/test/CodeGen/AMDGPU/ret.ll +++ b/llvm/test/CodeGen/AMDGPU/ret.ll @@ -18,13 +18,12 @@ define amdgpu_vs {float, float} @vgpr([9 x <16 x i8>] addrspace(2)* byval, i32 i } ; GCN-LABEL: {{^}}vgpr_literal: -; GCN: v_mov_b32_e32 v4, v0 +; GCN: exp 15, 0, 1, 1, 1, v0, v0, v0, v0 +; GCN: s_waitcnt expcnt(0) ; GCN-DAG: v_mov_b32_e32 v0, 1.0 ; GCN-DAG: v_mov_b32_e32 v1, 2.0 ; GCN-DAG: v_mov_b32_e32 v2, 4.0 ; GCN-DAG: v_mov_b32_e32 v3, -1.0 -; GCN: exp 15, 0, 1, 1, 1, v4, v4, v4, v4 -; GCN: s_waitcnt expcnt(0) ; GCN-NOT: s_endpgm define amdgpu_vs {float, float, float, float} @vgpr_literal([9 x <16 x i8>] addrspace(2)* byval, i32 inreg, i32 inreg, float) { call void @llvm.SI.export(i32 15, i32 1, i32 1, i32 0, i32 1, float %3, float %3, float %3, float %3) @@ -230,13 +229,13 @@ define amdgpu_vs {float, i32, float, i32, i32} @both([9 x <16 x i8>] addrspace(2 ; GCN-LABEL: {{^}}structure_literal: -; GCN: v_mov_b32_e32 v3, v0 +; GCN: exp 15, 0, 1, 1, 1, v0, v0, v0, v0 +; GCN: s_waitcnt expcnt(0) ; GCN-DAG: v_mov_b32_e32 v0, 1.0 ; GCN-DAG: s_mov_b32 s0, 2 ; GCN-DAG: s_mov_b32 s1, 3 ; GCN-DAG: v_mov_b32_e32 v1, 2.0 ; GCN-DAG: v_mov_b32_e32 v2, 4.0 -; GCN-DAG: exp 15, 0, 1, 1, 1, v3, v3, v3, v3 define amdgpu_vs {{float, i32}, {i32, <2 x float>}} @structure_literal([9 x <16 x i8>] addrspace(2)* byval, i32 inreg, i32 inreg, float) { call void @llvm.SI.export(i32 15, i32 1, i32 1, i32 0, i32 1, float %3, float %3, float %3, float %3) ret {{float, i32}, {i32, <2 x float>}} {{float, i32} {float 1.0, i32 2}, {i32, <2 x float>} {i32 3, <2 x float> <float 2.0, float 4.0>}} |
