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-rw-r--r--llvm/lib/Target/BPF/BPF.td6
-rw-r--r--llvm/lib/Target/BPF/BPFInstrInfo.td102
-rw-r--r--llvm/lib/Target/BPF/InstPrinter/BPFInstPrinter.cpp18
-rw-r--r--llvm/test/CodeGen/BPF/alu8.ll16
-rw-r--r--llvm/test/CodeGen/BPF/atomics.ll4
-rw-r--r--llvm/test/CodeGen/BPF/basictest.ll10
-rw-r--r--llvm/test/CodeGen/BPF/cc_args.ll48
-rw-r--r--llvm/test/CodeGen/BPF/cc_args_be.ll48
-rw-r--r--llvm/test/CodeGen/BPF/cc_ret.ll18
-rw-r--r--llvm/test/CodeGen/BPF/cmp.ll20
-rw-r--r--llvm/test/CodeGen/BPF/ex1.ll10
-rw-r--r--llvm/test/CodeGen/BPF/fi_ri.ll14
-rw-r--r--llvm/test/CodeGen/BPF/intrinsics.ll16
-rw-r--r--llvm/test/CodeGen/BPF/load.ll12
-rw-r--r--llvm/test/CodeGen/BPF/loops.ll10
-rw-r--r--llvm/test/CodeGen/BPF/sanity.ll36
-rw-r--r--llvm/test/CodeGen/BPF/setcc.ll24
-rw-r--r--llvm/test/CodeGen/BPF/shifts.ll30
-rw-r--r--llvm/test/CodeGen/BPF/sockex2.ll7
-rw-r--r--llvm/test/CodeGen/BPF/undef.ll60
20 files changed, 260 insertions, 249 deletions
diff --git a/llvm/lib/Target/BPF/BPF.td b/llvm/lib/Target/BPF/BPF.td
index 8493b0fd1e4..11abe520c50 100644
--- a/llvm/lib/Target/BPF/BPF.td
+++ b/llvm/lib/Target/BPF/BPF.td
@@ -25,14 +25,20 @@ def BPFInstPrinter : AsmWriter {
bit isMCAsmWriter = 1;
}
+def BPFAsmParser : AsmParser {
+ bit HasMnemonicFirst = 0;
+}
+
def BPFAsmParserVariant : AsmParserVariant {
int Variant = 0;
string Name = "BPF";
string BreakCharacters = ".";
+ string TokenizingCharacters = "#()[]=:.<>!+*";
}
def BPF : Target {
let InstructionSet = BPFInstrInfo;
let AssemblyWriters = [BPFInstPrinter];
+ let AssemblyParsers = [BPFAsmParser];
let AssemblyParserVariants = [BPFAsmParserVariant];
}
diff --git a/llvm/lib/Target/BPF/BPFInstrInfo.td b/llvm/lib/Target/BPF/BPFInstrInfo.td
index 6b73db87fa2..1f766bfe21e 100644
--- a/llvm/lib/Target/BPF/BPFInstrInfo.td
+++ b/llvm/lib/Target/BPF/BPFInstrInfo.td
@@ -81,7 +81,7 @@ def BPF_CC_GEU : PatLeaf<(imm),
// jump instructions
class JMP_RR<bits<4> Opc, string OpcodeStr, PatLeaf Cond>
: InstBPF<(outs), (ins GPR:$dst, GPR:$src, brtarget:$BrDst),
- !strconcat(OpcodeStr, "\t$dst, $src goto $BrDst"),
+ "if $dst "#OpcodeStr#" $src goto $BrDst",
[(BPFbrcc i64:$dst, i64:$src, Cond, bb:$BrDst)]> {
bits<4> op;
bits<1> BPFSrc;
@@ -102,7 +102,7 @@ class JMP_RR<bits<4> Opc, string OpcodeStr, PatLeaf Cond>
class JMP_RI<bits<4> Opc, string OpcodeStr, PatLeaf Cond>
: InstBPF<(outs), (ins GPR:$dst, i64imm:$imm, brtarget:$BrDst),
- !strconcat(OpcodeStr, "i\t$dst, $imm goto $BrDst"),
+ "if $dst "#OpcodeStr#" $imm goto $BrDst",
[(BPFbrcc i64:$dst, i64immSExt32:$imm, Cond, bb:$BrDst)]> {
bits<4> op;
bits<1> BPFSrc;
@@ -128,18 +128,18 @@ multiclass J<bits<4> Opc, string OpcodeStr, PatLeaf Cond> {
let isBranch = 1, isTerminator = 1, hasDelaySlot=0 in {
// cmp+goto instructions
-defm JEQ : J<0x1, "jeq", BPF_CC_EQ>;
-defm JUGT : J<0x2, "jgt", BPF_CC_GTU>;
-defm JUGE : J<0x3, "jge", BPF_CC_GEU>;
-defm JNE : J<0x5, "jne", BPF_CC_NE>;
-defm JSGT : J<0x6, "jsgt", BPF_CC_GT>;
-defm JSGE : J<0x7, "jsge", BPF_CC_GE>;
+defm JEQ : J<0x1, "==", BPF_CC_EQ>;
+defm JUGT : J<0x2, ">", BPF_CC_GTU>;
+defm JUGE : J<0x3, ">=", BPF_CC_GEU>;
+defm JNE : J<0x5, "!=", BPF_CC_NE>;
+defm JSGT : J<0x6, "s>", BPF_CC_GT>;
+defm JSGE : J<0x7, "s>=", BPF_CC_GE>;
}
// ALU instructions
class ALU_RI<bits<4> Opc, string OpcodeStr, SDNode OpNode>
: InstBPF<(outs GPR:$dst), (ins GPR:$src2, i64imm:$imm),
- !strconcat(OpcodeStr, "i\t$dst, $imm"),
+ "$dst "#OpcodeStr#" $imm",
[(set GPR:$dst, (OpNode GPR:$src2, i64immSExt32:$imm))]> {
bits<4> op;
bits<1> BPFSrc;
@@ -158,7 +158,7 @@ class ALU_RI<bits<4> Opc, string OpcodeStr, SDNode OpNode>
class ALU_RR<bits<4> Opc, string OpcodeStr, SDNode OpNode>
: InstBPF<(outs GPR:$dst), (ins GPR:$src2, GPR:$src),
- !strconcat(OpcodeStr, "\t$dst, $src"),
+ "$dst "#OpcodeStr#" $src",
[(set GPR:$dst, (OpNode i64:$src2, i64:$src))]> {
bits<4> op;
bits<1> BPFSrc;
@@ -182,22 +182,22 @@ multiclass ALU<bits<4> Opc, string OpcodeStr, SDNode OpNode> {
let Constraints = "$dst = $src2" in {
let isAsCheapAsAMove = 1 in {
- defm ADD : ALU<0x0, "add", add>;
- defm SUB : ALU<0x1, "sub", sub>;
- defm OR : ALU<0x4, "or", or>;
- defm AND : ALU<0x5, "and", and>;
- defm SLL : ALU<0x6, "sll", shl>;
- defm SRL : ALU<0x7, "srl", srl>;
- defm XOR : ALU<0xa, "xor", xor>;
- defm SRA : ALU<0xc, "sra", sra>;
+ defm ADD : ALU<0x0, "+=", add>;
+ defm SUB : ALU<0x1, "-=", sub>;
+ defm OR : ALU<0x4, "|=", or>;
+ defm AND : ALU<0x5, "&=", and>;
+ defm SLL : ALU<0x6, "<<=", shl>;
+ defm SRL : ALU<0x7, ">>=", srl>;
+ defm XOR : ALU<0xa, "^=", xor>;
+ defm SRA : ALU<0xc, "s>>=", sra>;
}
- defm MUL : ALU<0x2, "mul", mul>;
- defm DIV : ALU<0x3, "div", udiv>;
+ defm MUL : ALU<0x2, "*=", mul>;
+ defm DIV : ALU<0x3, "/=", udiv>;
}
class MOV_RR<string OpcodeStr>
: InstBPF<(outs GPR:$dst), (ins GPR:$src),
- !strconcat(OpcodeStr, "\t$dst, $src"),
+ "$dst "#OpcodeStr#" $src",
[]> {
bits<4> op;
bits<1> BPFSrc;
@@ -216,7 +216,7 @@ class MOV_RR<string OpcodeStr>
class MOV_RI<string OpcodeStr>
: InstBPF<(outs GPR:$dst), (ins i64imm:$imm),
- !strconcat(OpcodeStr, "\t$dst, $imm"),
+ "$dst "#OpcodeStr#" $imm",
[(set GPR:$dst, (i64 i64immSExt32:$imm))]> {
bits<4> op;
bits<1> BPFSrc;
@@ -235,7 +235,7 @@ class MOV_RI<string OpcodeStr>
class LD_IMM64<bits<4> Pseudo, string OpcodeStr>
: InstBPF<(outs GPR:$dst), (ins u64imm:$imm),
- !strconcat(OpcodeStr, "\t$dst, $imm"),
+ "$dst "#OpcodeStr#" ${imm}ll",
[(set GPR:$dst, (i64 imm:$imm))]> {
bits<3> mode;
@@ -256,9 +256,9 @@ class LD_IMM64<bits<4> Pseudo, string OpcodeStr>
}
let isReMaterializable = 1, isAsCheapAsAMove = 1 in {
-def LD_imm64 : LD_IMM64<0, "ld_64">;
-def MOV_rr : MOV_RR<"mov">;
-def MOV_ri : MOV_RI<"mov">;
+def LD_imm64 : LD_IMM64<0, "=">;
+def MOV_rr : MOV_RR<"=">;
+def MOV_ri : MOV_RI<"=">;
}
def FI_ri
@@ -296,7 +296,7 @@ def LD_pseudo
// STORE instructions
class STORE<bits<2> SizeOp, string OpcodeStr, list<dag> Pattern>
: InstBPF<(outs), (ins GPR:$src, MEMri:$addr),
- !strconcat(OpcodeStr, "\t$addr, $src"), Pattern> {
+ "*("#OpcodeStr#" *)($addr) = $src", Pattern> {
bits<3> mode;
bits<2> size;
bits<4> src;
@@ -316,15 +316,15 @@ class STORE<bits<2> SizeOp, string OpcodeStr, list<dag> Pattern>
class STOREi64<bits<2> Opc, string OpcodeStr, PatFrag OpNode>
: STORE<Opc, OpcodeStr, [(OpNode i64:$src, ADDRri:$addr)]>;
-def STW : STOREi64<0x0, "stw", truncstorei32>;
-def STH : STOREi64<0x1, "sth", truncstorei16>;
-def STB : STOREi64<0x2, "stb", truncstorei8>;
-def STD : STOREi64<0x3, "std", store>;
+def STW : STOREi64<0x0, "u32", truncstorei32>;
+def STH : STOREi64<0x1, "u16", truncstorei16>;
+def STB : STOREi64<0x2, "u8", truncstorei8>;
+def STD : STOREi64<0x3, "u64", store>;
// LOAD instructions
class LOAD<bits<2> SizeOp, string OpcodeStr, list<dag> Pattern>
: InstBPF<(outs GPR:$dst), (ins MEMri:$addr),
- !strconcat(OpcodeStr, "\t$dst, $addr"), Pattern> {
+ "$dst = *("#OpcodeStr#" *)($addr)", Pattern> {
bits<3> mode;
bits<2> size;
bits<4> dst;
@@ -344,14 +344,14 @@ class LOAD<bits<2> SizeOp, string OpcodeStr, list<dag> Pattern>
class LOADi64<bits<2> SizeOp, string OpcodeStr, PatFrag OpNode>
: LOAD<SizeOp, OpcodeStr, [(set i64:$dst, (OpNode ADDRri:$addr))]>;
-def LDW : LOADi64<0x0, "ldw", zextloadi32>;
-def LDH : LOADi64<0x1, "ldh", zextloadi16>;
-def LDB : LOADi64<0x2, "ldb", zextloadi8>;
-def LDD : LOADi64<0x3, "ldd", load>;
+def LDW : LOADi64<0x0, "u32", zextloadi32>;
+def LDH : LOADi64<0x1, "u16", zextloadi16>;
+def LDB : LOADi64<0x2, "u8", zextloadi8>;
+def LDD : LOADi64<0x3, "u64", load>;
class BRANCH<bits<4> Opc, string OpcodeStr, list<dag> Pattern>
: InstBPF<(outs), (ins brtarget:$BrDst),
- !strconcat(OpcodeStr, "\t$BrDst"), Pattern> {
+ !strconcat(OpcodeStr, " $BrDst"), Pattern> {
bits<4> op;
bits<16> BrDst;
bits<1> BPFSrc;
@@ -367,7 +367,7 @@ class BRANCH<bits<4> Opc, string OpcodeStr, list<dag> Pattern>
class CALL<string OpcodeStr>
: InstBPF<(outs), (ins calltarget:$BrDst),
- !strconcat(OpcodeStr, "\t$BrDst"), []> {
+ !strconcat(OpcodeStr, " $BrDst"), []> {
bits<4> op;
bits<32> BrDst;
bits<1> BPFSrc;
@@ -383,7 +383,7 @@ class CALL<string OpcodeStr>
// Jump always
let isBranch = 1, isTerminator = 1, hasDelaySlot=0, isBarrier = 1 in {
- def JMP : BRANCH<0x0, "jmp", [(br bb:$BrDst)]>;
+ def JMP : BRANCH<0x0, "goto", [(br bb:$BrDst)]>;
}
// Jump and link
@@ -432,7 +432,7 @@ class RET<string OpcodeStr>
let isReturn = 1, isTerminator = 1, hasDelaySlot=0, isBarrier = 1,
isNotDuplicable = 1 in {
- def RET : RET<"ret">;
+ def RET : RET<"exit">;
}
// ADJCALLSTACKDOWN/UP pseudo insns
@@ -472,7 +472,7 @@ def : Pat<(extloadi32 ADDRri:$src), (i64 (LDW ADDRri:$src))>;
// Atomics
class XADD<bits<2> SizeOp, string OpcodeStr, PatFrag OpNode>
: InstBPF<(outs GPR:$dst), (ins MEMri:$addr, GPR:$val),
- !strconcat(OpcodeStr, "\t$dst, $addr, $val"),
+ "lock *("#OpcodeStr#" *)($addr) += $val",
[(set GPR:$dst, (OpNode ADDRri:$addr, GPR:$val))]> {
bits<3> mode;
bits<2> size;
@@ -491,8 +491,8 @@ class XADD<bits<2> SizeOp, string OpcodeStr, PatFrag OpNode>
}
let Constraints = "$dst = $val" in {
-def XADD32 : XADD<0, "xadd32", atomic_load_add_32>;
-def XADD64 : XADD<3, "xadd64", atomic_load_add_64>;
+def XADD32 : XADD<0, "u32", atomic_load_add_32>;
+def XADD64 : XADD<3, "u64", atomic_load_add_64>;
// undefined def XADD16 : XADD<1, "xadd16", atomic_load_add_16>;
// undefined def XADD8 : XADD<2, "xadd8", atomic_load_add_8>;
}
@@ -528,7 +528,7 @@ let Defs = [R0, R1, R2, R3, R4, R5], Uses = [R6], hasSideEffects = 1,
hasExtraDefRegAllocReq = 1, hasExtraSrcRegAllocReq = 1, mayLoad = 1 in {
class LOAD_ABS<bits<2> SizeOp, string OpcodeStr, Intrinsic OpNode>
: InstBPF<(outs), (ins GPR:$skb, i64imm:$imm),
- !strconcat(OpcodeStr, "\tr0, $skb.data + $imm"),
+ "r0 = *("#OpcodeStr#" *)skb[$imm]",
[(set R0, (OpNode GPR:$skb, i64immSExt32:$imm))]> {
bits<3> mode;
bits<2> size;
@@ -545,7 +545,7 @@ class LOAD_ABS<bits<2> SizeOp, string OpcodeStr, Intrinsic OpNode>
class LOAD_IND<bits<2> SizeOp, string OpcodeStr, Intrinsic OpNode>
: InstBPF<(outs), (ins GPR:$skb, GPR:$val),
- !strconcat(OpcodeStr, "\tr0, $skb.data + $val"),
+ "r0 = *("#OpcodeStr#" *)skb[$val]",
[(set R0, (OpNode GPR:$skb, GPR:$val))]> {
bits<3> mode;
bits<2> size;
@@ -561,10 +561,10 @@ class LOAD_IND<bits<2> SizeOp, string OpcodeStr, Intrinsic OpNode>
}
}
-def LD_ABS_B : LOAD_ABS<2, "ldabs_b", int_bpf_load_byte>;
-def LD_ABS_H : LOAD_ABS<1, "ldabs_h", int_bpf_load_half>;
-def LD_ABS_W : LOAD_ABS<0, "ldabs_w", int_bpf_load_word>;
+def LD_ABS_B : LOAD_ABS<2, "u8", int_bpf_load_byte>;
+def LD_ABS_H : LOAD_ABS<1, "u16", int_bpf_load_half>;
+def LD_ABS_W : LOAD_ABS<0, "u32", int_bpf_load_word>;
-def LD_IND_B : LOAD_IND<2, "ldind_b", int_bpf_load_byte>;
-def LD_IND_H : LOAD_IND<1, "ldind_h", int_bpf_load_half>;
-def LD_IND_W : LOAD_IND<0, "ldind_w", int_bpf_load_word>;
+def LD_IND_B : LOAD_IND<2, "u8", int_bpf_load_byte>;
+def LD_IND_H : LOAD_IND<1, "u16", int_bpf_load_half>;
+def LD_IND_W : LOAD_IND<0, "u32", int_bpf_load_word>;
diff --git a/llvm/lib/Target/BPF/InstPrinter/BPFInstPrinter.cpp b/llvm/lib/Target/BPF/InstPrinter/BPFInstPrinter.cpp
index 552288b819d..ffd29f3ea99 100644
--- a/llvm/lib/Target/BPF/InstPrinter/BPFInstPrinter.cpp
+++ b/llvm/lib/Target/BPF/InstPrinter/BPFInstPrinter.cpp
@@ -67,15 +67,21 @@ void BPFInstPrinter::printMemOperand(const MCInst *MI, int OpNo, raw_ostream &O,
const char *Modifier) {
const MCOperand &RegOp = MI->getOperand(OpNo);
const MCOperand &OffsetOp = MI->getOperand(OpNo + 1);
- // offset
- if (OffsetOp.isImm())
- O << formatDec(OffsetOp.getImm());
- else
- assert(0 && "Expected an immediate");
// register
assert(RegOp.isReg() && "Register operand not a register");
- O << '(' << getRegisterName(RegOp.getReg()) << ')';
+ O << getRegisterName(RegOp.getReg());
+
+ // offset
+ if (OffsetOp.isImm()) {
+ auto Imm = OffsetOp.getImm();
+ if (Imm >= 0)
+ O << " + " << formatDec(Imm);
+ else
+ O << " - " << formatDec(-Imm);
+ } else {
+ assert(0 && "Expected an immediate");
+ }
}
void BPFInstPrinter::printImm64Operand(const MCInst *MI, unsigned OpNo,
diff --git a/llvm/test/CodeGen/BPF/alu8.ll b/llvm/test/CodeGen/BPF/alu8.ll
index c1c2bd29f24..73e7a8cf77f 100644
--- a/llvm/test/CodeGen/BPF/alu8.ll
+++ b/llvm/test/CodeGen/BPF/alu8.ll
@@ -2,36 +2,36 @@
define i8 @mov(i8 %a, i8 %b) nounwind {
; CHECK-LABEL: mov:
-; CHECK: mov r0, r2 # encoding: [0xbf,0x20,0x00,0x00,0x00,0x00,0x00,0x00]
-; CHECK: ret # encoding: [0x95,0x00,0x00,0x00,0x00,0x00,0x00,0x00]
+; CHECK: r0 = r2 # encoding: [0xbf,0x20,0x00,0x00,0x00,0x00,0x00,0x00]
+; CHECK: exit # encoding: [0x95,0x00,0x00,0x00,0x00,0x00,0x00,0x00]
ret i8 %b
}
define i8 @add(i8 %a, i8 %b) nounwind {
; CHECK-LABEL: add:
-; CHECK: add r1, r2 # encoding: [0x0f,0x21,0x00,0x00,0x00,0x00,0x00,0x00]
-; CHECK: mov r0, r1 # encoding: [0xbf,0x10,0x00,0x00,0x00,0x00,0x00,0x00]
+; CHECK: r1 += r2 # encoding: [0x0f,0x21,0x00,0x00,0x00,0x00,0x00,0x00]
+; CHECK: r0 = r1 # encoding: [0xbf,0x10,0x00,0x00,0x00,0x00,0x00,0x00]
%1 = add i8 %a, %b
ret i8 %1
}
define i8 @and(i8 %a, i8 %b) nounwind {
; CHECK-LABEL: and:
-; CHECK: and r1, r2 # encoding: [0x5f,0x21,0x00,0x00,0x00,0x00,0x00,0x00]
+; CHECK: r1 &= r2 # encoding: [0x5f,0x21,0x00,0x00,0x00,0x00,0x00,0x00]
%1 = and i8 %a, %b
ret i8 %1
}
define i8 @bis(i8 %a, i8 %b) nounwind {
; CHECK-LABEL: bis:
-; CHECK: or r1, r2 # encoding: [0x4f,0x21,0x00,0x00,0x00,0x00,0x00,0x00]
+; CHECK: r1 |= r2 # encoding: [0x4f,0x21,0x00,0x00,0x00,0x00,0x00,0x00]
%1 = or i8 %a, %b
ret i8 %1
}
define i8 @xorand(i8 %a, i8 %b) nounwind {
; CHECK-LABEL: xorand:
-; CHECK: xori r2, -1 # encoding: [0xa7,0x02,0x00,0x00,0xff,0xff,0xff,0xff]
+; CHECK: r2 ^= -1 # encoding: [0xa7,0x02,0x00,0x00,0xff,0xff,0xff,0xff]
%1 = xor i8 %b, -1
%2 = and i8 %a, %1
ret i8 %2
@@ -39,7 +39,7 @@ define i8 @xorand(i8 %a, i8 %b) nounwind {
define i8 @xor(i8 %a, i8 %b) nounwind {
; CHECK-LABEL: xor:
-; CHECK: xor r1, r2 # encoding: [0xaf,0x21,0x00,0x00,0x00,0x00,0x00,0x00]
+; CHECK: r1 ^= r2 # encoding: [0xaf,0x21,0x00,0x00,0x00,0x00,0x00,0x00]
%1 = xor i8 %a, %b
ret i8 %1
}
diff --git a/llvm/test/CodeGen/BPF/atomics.ll b/llvm/test/CodeGen/BPF/atomics.ll
index a2e17d29196..c24dd65d6eb 100644
--- a/llvm/test/CodeGen/BPF/atomics.ll
+++ b/llvm/test/CodeGen/BPF/atomics.ll
@@ -1,7 +1,7 @@
; RUN: llc < %s -march=bpfel -verify-machineinstrs -show-mc-encoding | FileCheck %s
; CHECK-LABEL: test_load_add_32
-; CHECK: xadd32
+; CHECK: lock *(u32 *)
; CHECK: encoding: [0xc3
define void @test_load_add_32(i32* %p, i32 zeroext %v) {
entry:
@@ -10,7 +10,7 @@ entry:
}
; CHECK-LABEL: test_load_add_64
-; CHECK: xadd64
+; CHECK: lock *(u64 *)
; CHECK: encoding: [0xdb
define void @test_load_add_64(i64* %p, i64 zeroext %v) {
entry:
diff --git a/llvm/test/CodeGen/BPF/basictest.ll b/llvm/test/CodeGen/BPF/basictest.ll
index 82feb43d005..13a49806ed4 100644
--- a/llvm/test/CodeGen/BPF/basictest.ll
+++ b/llvm/test/CodeGen/BPF/basictest.ll
@@ -4,12 +4,12 @@ define i32 @test0(i32 %X) {
%tmp.1 = add i32 %X, 1
ret i32 %tmp.1
; CHECK-LABEL: test0:
-; CHECK: addi r1, 1
+; CHECK: r1 += 1
}
; CHECK-LABEL: store_imm:
-; CHECK: stw 0(r1), r{{[03]}}
-; CHECK: stw 4(r2), r{{[03]}}
+; CHECK: *(u32 *)(r1 + 0) = r{{[03]}}
+; CHECK: *(u32 *)(r2 + 4) = r{{[03]}}
define i32 @store_imm(i32* %a, i32* %b) {
entry:
store i32 0, i32* %a, align 4
@@ -23,6 +23,6 @@ define zeroext i8 @loadG() {
%tmp = load i8, i8* @G
ret i8 %tmp
; CHECK-LABEL: loadG:
-; CHECK: ld_64 r1
-; CHECK: ldb r0, 0(r1)
+; CHECK: r1 =
+; CHECK: r0 = *(u8 *)(r1 + 0)
}
diff --git a/llvm/test/CodeGen/BPF/cc_args.ll b/llvm/test/CodeGen/BPF/cc_args.ll
index 8e3f8604ac8..4ad7a22c7e2 100644
--- a/llvm/test/CodeGen/BPF/cc_args.ll
+++ b/llvm/test/CodeGen/BPF/cc_args.ll
@@ -4,32 +4,32 @@ define void @test() #0 {
entry:
; CHECK: test:
-; CHECK: mov r1, 123 # encoding: [0xb7,0x01,0x00,0x00,0x7b,0x00,0x00,0x00]
+; CHECK: r1 = 123 # encoding: [0xb7,0x01,0x00,0x00,0x7b,0x00,0x00,0x00]
; CHECK: call f_i16
call void @f_i16(i16 123)
-; CHECK: mov r1, 12345678 # encoding: [0xb7,0x01,0x00,0x00,0x4e,0x61,0xbc,0x00]
+; CHECK: r1 = 12345678 # encoding: [0xb7,0x01,0x00,0x00,0x4e,0x61,0xbc,0x00]
; CHECK: call f_i32
call void @f_i32(i32 12345678)
-; CHECK: ld_64 r1, 72623859790382856 # encoding: [0x18,0x01,0x00,0x00,0x08,0x07,0x06,0x05,0x00,0x00,0x00,0x00,0x04,0x03,0x02,0x01]
+; CHECK: r1 = 72623859790382856ll # encoding: [0x18,0x01,0x00,0x00,0x08,0x07,0x06,0x05,0x00,0x00,0x00,0x00,0x04,0x03,0x02,0x01]
; CHECK: call f_i64
call void @f_i64(i64 72623859790382856)
-; CHECK: mov r1, 1234
-; CHECK: mov r2, 5678
+; CHECK: r1 = 1234
+; CHECK: r2 = 5678
; CHECK: call f_i32_i32
call void @f_i32_i32(i32 1234, i32 5678)
-; CHECK: mov r1, 2
-; CHECK: mov r2, 3
-; CHECK: mov r3, 4
+; CHECK: r1 = 2
+; CHECK: r2 = 3
+; CHECK: r3 = 4
; CHECK: call f_i16_i32_i16
call void @f_i16_i32_i16(i16 2, i32 3, i16 4)
-; CHECK: mov r1, 5
-; CHECK: ld_64 r2, 7262385979038285
-; CHECK: mov r3, 6
+; CHECK: r1 = 5
+; CHECK: r2 = 7262385979038285ll
+; CHECK: r3 = 6
; CHECK: call f_i16_i64_i16
call void @f_i16_i64_i16(i16 5, i64 7262385979038285, i16 6)
@@ -42,54 +42,54 @@ entry:
define void @f_i16(i16 %a) #0 {
; CHECK: f_i16:
-; CHECK: sth 0(r2), r1 # encoding: [0x6b,0x12,0x00,0x00,0x00,0x00,0x00,0x00]
+; CHECK: *(u16 *)(r2 + 0) = r1 # encoding: [0x6b,0x12,0x00,0x00,0x00,0x00,0x00,0x00]
store volatile i16 %a, i16* @g_i16, align 2
ret void
}
define void @f_i32(i32 %a) #0 {
; CHECK: f_i32:
-; CHECK: sth 0(r2), r1 # encoding: [0x6b,0x12,0x00,0x00,0x00,0x00,0x00,0x00]
-; CHECK: sth 2(r2), r1 # encoding: [0x6b,0x12,0x02,0x00,0x00,0x00,0x00,0x00]
+; CHECK: *(u16 *)(r2 + 0) = r1 # encoding: [0x6b,0x12,0x00,0x00,0x00,0x00,0x00,0x00]
+; CHECK: *(u16 *)(r2 + 2) = r1 # encoding: [0x6b,0x12,0x02,0x00,0x00,0x00,0x00,0x00]
store volatile i32 %a, i32* @g_i32, align 2
ret void
}
define void @f_i64(i64 %a) #0 {
; CHECK: f_i64:
-; CHECK: stw 0(r2), r1
-; CHECK: stw 4(r2), r1 # encoding: [0x63,0x12,0x04,0x00,0x00,0x00,0x00,0x00]
+; CHECK: *(u32 *)(r2 + 0) = r1
+; CHECK: *(u32 *)(r2 + 4) = r1 # encoding: [0x63,0x12,0x04,0x00,0x00,0x00,0x00,0x00]
store volatile i64 %a, i64* @g_i64, align 2
ret void
}
define void @f_i32_i32(i32 %a, i32 %b) #0 {
; CHECK: f_i32_i32:
-; CHECK: stw 0(r3), r1
+; CHECK: *(u32 *)(r3 + 0) = r1
store volatile i32 %a, i32* @g_i32, align 4
-; CHECK: stw 0(r3), r2
+; CHECK: *(u32 *)(r3 + 0) = r2
store volatile i32 %b, i32* @g_i32, align 4
ret void
}
define void @f_i16_i32_i16(i16 %a, i32 %b, i16 %c) #0 {
; CHECK: f_i16_i32_i16:
-; CHECK: sth 0(r4), r1
+; CHECK: *(u16 *)(r4 + 0) = r1
store volatile i16 %a, i16* @g_i16, align 2
-; CHECK: stw 0(r1), r2
+; CHECK: *(u32 *)(r1 + 0) = r2
store volatile i32 %b, i32* @g_i32, align 4
-; CHECK: sth 0(r4), r3
+; CHECK: *(u16 *)(r4 + 0) = r3
store volatile i16 %c, i16* @g_i16, align 2
ret void
}
define void @f_i16_i64_i16(i16 %a, i64 %b, i16 %c) #0 {
; CHECK: f_i16_i64_i16:
-; CHECK: sth 0(r4), r1
+; CHECK: *(u16 *)(r4 + 0) = r1
store volatile i16 %a, i16* @g_i16, align 2
-; CHECK: std 0(r1), r2 # encoding: [0x7b,0x21,0x00,0x00,0x00,0x00,0x00,0x00]
+; CHECK: *(u64 *)(r1 + 0) = r2 # encoding: [0x7b,0x21,0x00,0x00,0x00,0x00,0x00,0x00]
store volatile i64 %b, i64* @g_i64, align 8
-; CHECK: sth 0(r4), r3
+; CHECK: *(u16 *)(r4 + 0) = r3
store volatile i16 %c, i16* @g_i16, align 2
ret void
}
diff --git a/llvm/test/CodeGen/BPF/cc_args_be.ll b/llvm/test/CodeGen/BPF/cc_args_be.ll
index 59a7439728b..4d1efccf516 100644
--- a/llvm/test/CodeGen/BPF/cc_args_be.ll
+++ b/llvm/test/CodeGen/BPF/cc_args_be.ll
@@ -5,32 +5,32 @@ define void @test() #0 {
entry:
; CHECK: test:
-; CHECK: mov r1, 123 # encoding: [0xb7,0x10,0x00,0x00,0x00,0x00,0x00,0x7b]
+; CHECK: r1 = 123 # encoding: [0xb7,0x10,0x00,0x00,0x00,0x00,0x00,0x7b]
; CHECK: call f_i16
call void @f_i16(i16 123)
-; CHECK: mov r1, 12345678 # encoding: [0xb7,0x10,0x00,0x00,0x00,0xbc,0x61,0x4e]
+; CHECK: r1 = 12345678 # encoding: [0xb7,0x10,0x00,0x00,0x00,0xbc,0x61,0x4e]
; CHECK: call f_i32
call void @f_i32(i32 12345678)
-; CHECK: ld_64 r1, 72623859790382856 # encoding: [0x18,0x10,0x00,0x00,0x05,0x06,0x07,0x08,0x00,0x00,0x00,0x00,0x01,0x02,0x03,0x04]
+; CHECK: r1 = 72623859790382856ll # encoding: [0x18,0x10,0x00,0x00,0x05,0x06,0x07,0x08,0x00,0x00,0x00,0x00,0x01,0x02,0x03,0x04]
; CHECK: call f_i64
call void @f_i64(i64 72623859790382856)
-; CHECK: mov r1, 1234
-; CHECK: mov r2, 5678
+; CHECK: r1 = 1234
+; CHECK: r2 = 5678
; CHECK: call f_i32_i32
call void @f_i32_i32(i32 1234, i32 5678)
-; CHECK: mov r1, 2
-; CHECK: mov r2, 3
-; CHECK: mov r3, 4
+; CHECK: r1 = 2
+; CHECK: r2 = 3
+; CHECK: r3 = 4
; CHECK: call f_i16_i32_i16
call void @f_i16_i32_i16(i16 2, i32 3, i16 4)
-; CHECK: mov r1, 5
-; CHECK: ld_64 r2, 7262385979038285
-; CHECK: mov r3, 6
+; CHECK: r1 = 5
+; CHECK: r2 = 7262385979038285ll
+; CHECK: r3 = 6
; CHECK: call f_i16_i64_i16
call void @f_i16_i64_i16(i16 5, i64 7262385979038285, i16 6)
@@ -43,54 +43,54 @@ entry:
define void @f_i16(i16 %a) #0 {
; CHECK: f_i16:
-; CHECK: sth 0(r2), r1 # encoding: [0x6b,0x21,0x00,0x00,0x00,0x00,0x00,0x00]
+; CHECK: *(u16 *)(r2 + 0) = r1 # encoding: [0x6b,0x21,0x00,0x00,0x00,0x00,0x00,0x00]
store volatile i16 %a, i16* @g_i16, align 2
ret void
}
define void @f_i32(i32 %a) #0 {
; CHECK: f_i32:
-; CHECK: sth 2(r2), r1 # encoding: [0x6b,0x21,0x00,0x02,0x00,0x00,0x00,0x00]
-; CHECK: sth 0(r2), r1 # encoding: [0x6b,0x21,0x00,0x00,0x00,0x00,0x00,0x00]
+; CHECK: *(u16 *)(r2 + 2) = r1 # encoding: [0x6b,0x21,0x00,0x02,0x00,0x00,0x00,0x00]
+; CHECK: *(u16 *)(r2 + 0) = r1 # encoding: [0x6b,0x21,0x00,0x00,0x00,0x00,0x00,0x00]
store volatile i32 %a, i32* @g_i32, align 2
ret void
}
define void @f_i64(i64 %a) #0 {
; CHECK: f_i64:
-; CHECK: stw 4(r2), r1 # encoding: [0x63,0x21,0x00,0x04,0x00,0x00,0x00,0x00]
-; CHECK: stw 0(r2), r1
+; CHECK: *(u32 *)(r2 + 4) = r1 # encoding: [0x63,0x21,0x00,0x04,0x00,0x00,0x00,0x00]
+; CHECK: *(u32 *)(r2 + 0) = r1
store volatile i64 %a, i64* @g_i64, align 2
ret void
}
define void @f_i32_i32(i32 %a, i32 %b) #0 {
; CHECK: f_i32_i32:
-; CHECK: stw 0(r3), r1
+; CHECK: *(u32 *)(r3 + 0) = r1
store volatile i32 %a, i32* @g_i32, align 4
-; CHECK: stw 0(r3), r2
+; CHECK: *(u32 *)(r3 + 0) = r2
store volatile i32 %b, i32* @g_i32, align 4
ret void
}
define void @f_i16_i32_i16(i16 %a, i32 %b, i16 %c) #0 {
; CHECK: f_i16_i32_i16:
-; CHECK: sth 0(r4), r1
+; CHECK: *(u16 *)(r4 + 0) = r1
store volatile i16 %a, i16* @g_i16, align 2
-; CHECK: stw 0(r1), r2
+; CHECK: *(u32 *)(r1 + 0) = r2
store volatile i32 %b, i32* @g_i32, align 4
-; CHECK: sth 0(r4), r3
+; CHECK: *(u16 *)(r4 + 0) = r3
store volatile i16 %c, i16* @g_i16, align 2
ret void
}
define void @f_i16_i64_i16(i16 %a, i64 %b, i16 %c) #0 {
; CHECK: f_i16_i64_i16:
-; CHECK: sth 0(r4), r1
+; CHECK: *(u16 *)(r4 + 0) = r1
store volatile i16 %a, i16* @g_i16, align 2
-; CHECK: std 0(r1), r2 # encoding: [0x7b,0x12,0x00,0x00,0x00,0x00,0x00,0x00]
+; CHECK: *(u64 *)(r1 + 0) = r2 # encoding: [0x7b,0x12,0x00,0x00,0x00,0x00,0x00,0x00]
store volatile i64 %b, i64* @g_i64, align 8
-; CHECK: sth 0(r4), r3
+; CHECK: *(u16 *)(r4 + 0) = r3
store volatile i16 %c, i16* @g_i16, align 2
ret void
}
diff --git a/llvm/test/CodeGen/BPF/cc_ret.ll b/llvm/test/CodeGen/BPF/cc_ret.ll
index 09574922f32..7bd01adc6de 100644
--- a/llvm/test/CodeGen/BPF/cc_ret.ll
+++ b/llvm/test/CodeGen/BPF/cc_ret.ll
@@ -5,17 +5,17 @@ entry:
; CHECK: test:
; CHECK: call f_i16
-; CHECK: sth 0(r1), r0
+; CHECK: *(u16 *)(r1 + 0) = r0
%0 = call i16 @f_i16()
store volatile i16 %0, i16* @g_i16
; CHECK: call f_i32
-; CHECK: stw 0(r1), r0
+; CHECK: *(u32 *)(r1 + 0) = r0
%1 = call i32 @f_i32()
store volatile i32 %1, i32* @g_i32
; CHECK: call f_i64
-; CHECK: std 0(r1), r0
+; CHECK: *(u64 *)(r1 + 0) = r0
%2 = call i64 @f_i64()
store volatile i64 %2, i64* @g_i64
@@ -28,21 +28,21 @@ entry:
define i16 @f_i16() #0 {
; CHECK: f_i16:
-; CHECK: mov r0, 1
-; CHECK: ret
+; CHECK: r0 = 1
+; CHECK: exit
ret i16 1
}
define i32 @f_i32() #0 {
; CHECK: f_i32:
-; CHECK: mov r0, 16909060
-; CHECK: ret
+; CHECK: r0 = 16909060
+; CHECK: exit
ret i32 16909060
}
define i64 @f_i64() #0 {
; CHECK: f_i64:
-; CHECK: ld_64 r0, 72623859790382856
-; CHECK: ret
+; CHECK: r0 = 72623859790382856ll
+; CHECK: exit
ret i64 72623859790382856
}
diff --git a/llvm/test/CodeGen/BPF/cmp.ll b/llvm/test/CodeGen/BPF/cmp.ll
index b353f90ab56..66345ab52a1 100644
--- a/llvm/test/CodeGen/BPF/cmp.ll
+++ b/llvm/test/CodeGen/BPF/cmp.ll
@@ -17,7 +17,7 @@ define signext i8 @foo_cmp1(i8 signext %a, i8 signext %b) #0 {
%.0 = phi i8 [ %3, %2 ], [ %5, %4 ]
ret i8 %.0
; CHECK-LABEL:foo_cmp1:
-; CHECK: jsge r2, r1
+; CHECK: if r2 s>= r1
}
; Function Attrs: nounwind readnone uwtable
@@ -37,7 +37,7 @@ define signext i8 @foo_cmp2(i8 signext %a, i8 signext %b) #0 {
%.0 = phi i8 [ %3, %2 ], [ %5, %4 ]
ret i8 %.0
; CHECK-LABEL:foo_cmp2:
-; CHECK: jsgt r2, r1
+; CHECK: if r2 s> r1
}
; Function Attrs: nounwind readnone uwtable
@@ -57,7 +57,7 @@ define signext i8 @foo_cmp3(i8 signext %a, i8 signext %b) #0 {
%.0 = phi i8 [ %3, %2 ], [ %5, %4 ]
ret i8 %.0
; CHECK-LABEL:foo_cmp3:
-; CHECK: jsge r1, r2
+; CHECK: if r1 s>= r2
}
; Function Attrs: nounwind readnone uwtable
@@ -77,7 +77,7 @@ define signext i8 @foo_cmp4(i8 signext %a, i8 signext %b) #0 {
%.0 = phi i8 [ %3, %2 ], [ %5, %4 ]
ret i8 %.0
; CHECK-LABEL:foo_cmp4:
-; CHECK: jsgt r1, r2
+; CHECK: if r1 s> r2
}
; Function Attrs: nounwind readnone uwtable
@@ -86,9 +86,9 @@ define signext i8 @min(i8 signext %a, i8 signext %b) #0 {
%a.b = select i1 %1, i8 %a, i8 %b
ret i8 %a.b
; CHECK-LABEL:min:
-; CHECK: jsgt r2, r1
-; CHECK: mov r1, r2
-; CHECK: mov r0, r1
+; CHECK: if r2 s> r1
+; CHECK: r1 = r2
+; CHECK: r0 = r1
}
; Function Attrs: nounwind readnone uwtable
@@ -97,7 +97,7 @@ define zeroext i8 @minu(i8 zeroext %a, i8 zeroext %b) #0 {
%a.b = select i1 %1, i8 %a, i8 %b
ret i8 %a.b
; CHECK-LABEL:minu:
-; CHECK: jgt r3, r1
+; CHECK: if r3 > r1
}
; Function Attrs: nounwind readnone uwtable
@@ -106,7 +106,7 @@ define signext i8 @max(i8 signext %a, i8 signext %b) #0 {
%a.b = select i1 %1, i8 %a, i8 %b
ret i8 %a.b
; CHECK-LABEL:max:
-; CHECK: jsgt r1, r2
+; CHECK: if r1 s> r2
}
; Function Attrs: nounwind readnone uwtable
@@ -115,5 +115,5 @@ define signext i8 @meq(i8 signext %a, i8 signext %b, i8 signext %c) #0 {
%c.a = select i1 %1, i8 %c, i8 %a
ret i8 %c.a
; CHECK-LABEL:meq:
-; CHECK: jeq r1, r2
+; CHECK: if r1 == r2
}
diff --git a/llvm/test/CodeGen/BPF/ex1.ll b/llvm/test/CodeGen/BPF/ex1.ll
index 546e5d49da6..2f77884f5ef 100644
--- a/llvm/test/CodeGen/BPF/ex1.ll
+++ b/llvm/test/CodeGen/BPF/ex1.ll
@@ -30,12 +30,12 @@ define i32 @bpf_prog1(%struct.bpf_context* nocapture %ctx) #0 section "events/ne
; CHECK-LABEL: bpf_prog1:
; CHECK: call 4
; CHECK: call 9
-; CHECK: jnei r0, 0
-; CHECK: mov r1, 622884453
-; CHECK: ld_64 r1, 7214898703899978611
+; CHECK: if r0 != 0
+; CHECK: r1 = 622884453
+; CHECK: r1 = 7214898703899978611ll
; CHECK: call 11
-; CHECK: mov r0, 0
-; CHECK: ret
+; CHECK: r0 = 0
+; CHECK: exit
br label %13
; <label>:13 ; preds = %10, %0
diff --git a/llvm/test/CodeGen/BPF/fi_ri.ll b/llvm/test/CodeGen/BPF/fi_ri.ll
index 64773b429fb..12452988e8a 100644
--- a/llvm/test/CodeGen/BPF/fi_ri.ll
+++ b/llvm/test/CodeGen/BPF/fi_ri.ll
@@ -6,15 +6,15 @@
define i32 @test() #0 {
%key = alloca %struct.key_t, align 4
%1 = bitcast %struct.key_t* %key to i8*
-; CHECK: mov r1, 0
-; CHECK: stw -8(r10), r1
-; CHECK: std -16(r10), r1
-; CHECK: std -24(r10), r1
+; CHECK: r1 = 0
+; CHECK: *(u32 *)(r10 - 8) = r1
+; CHECK: *(u64 *)(r10 - 16) = r1
+; CHECK: *(u64 *)(r10 - 24) = r1
call void @llvm.memset.p0i8.i64(i8* %1, i8 0, i64 20, i32 4, i1 false)
-; CHECK: mov r1, r10
-; CHECK: addi r1, -20
+; CHECK: r1 = r10
+; CHECK: r1 += -20
%2 = getelementptr inbounds %struct.key_t, %struct.key_t* %key, i64 0, i32 1, i64 0
-; CHECK: call test1
+; CHECK: call test1
call void @test1(i8* %2) #3
ret i32 0
}
diff --git a/llvm/test/CodeGen/BPF/intrinsics.ll b/llvm/test/CodeGen/BPF/intrinsics.ll
index 483473e922f..e7a9de88cbb 100644
--- a/llvm/test/CodeGen/BPF/intrinsics.ll
+++ b/llvm/test/CodeGen/BPF/intrinsics.ll
@@ -13,8 +13,8 @@ define i32 @ld_b(i64 %foo, i64* nocapture %bar, i8* %ctx, i8* %ctx2) #0 {
%9 = trunc i64 %8 to i32
ret i32 %9
; CHECK-LABEL: ld_b:
-; CHECK: ldabs_b r0, r6.data + 123
-; CHECK: ldind_b r0, r6.data
+; CHECK: r0 = *(u8 *)skb[123]
+; CHECK: r0 = *(u8 *)skb[r
}
declare i64 @llvm.bpf.load.byte(i8*, i64) #1
@@ -28,8 +28,8 @@ define i32 @ld_h(i8* %ctx, i8* %ctx2, i32 %foo) #0 {
%5 = trunc i64 %4 to i32
ret i32 %5
; CHECK-LABEL: ld_h:
-; CHECK: ldind_h r0, r6.data
-; CHECK: ldabs_h r0, r6.data + 123
+; CHECK: r0 = *(u16 *)skb[r
+; CHECK: r0 = *(u16 *)skb[123]
}
declare i64 @llvm.bpf.load.half(i8*, i64) #1
@@ -43,8 +43,8 @@ define i32 @ld_w(i8* %ctx, i8* %ctx2, i32 %foo) #0 {
%5 = trunc i64 %4 to i32
ret i32 %5
; CHECK-LABEL: ld_w:
-; CHECK: ldind_w r0, r6.data
-; CHECK: ldabs_w r0, r6.data + 123
+; CHECK: r0 = *(u32 *)skb[r
+; CHECK: r0 = *(u32 *)skb[123]
}
declare i64 @llvm.bpf.load.word(i8*, i64) #1
@@ -78,9 +78,9 @@ entry:
; CHECK-LABEL: bswap:
; CHECK: bswap64 r1 # encoding: [0xdc,0x01,0x00,0x00,0x40,0x00,0x00,0x00]
; CHECK: bswap32 r2 # encoding: [0xdc,0x02,0x00,0x00,0x20,0x00,0x00,0x00]
-; CHECK: add r2, r1 # encoding: [0x0f,0x12,0x00,0x00,0x00,0x00,0x00,0x00]
+; CHECK: r2 += r1 # encoding: [0x0f,0x12,0x00,0x00,0x00,0x00,0x00,0x00]
; CHECK: bswap16 r3 # encoding: [0xdc,0x03,0x00,0x00,0x10,0x00,0x00,0x00]
-; CHECK: add r2, r3 # encoding: [0x0f,0x32,0x00,0x00,0x00,0x00,0x00,0x00]
+; CHECK: r2 += r3 # encoding: [0x0f,0x32,0x00,0x00,0x00,0x00,0x00,0x00]
}
declare i64 @llvm.bswap.i64(i64) #1
diff --git a/llvm/test/CodeGen/BPF/load.ll b/llvm/test/CodeGen/BPF/load.ll
index d4ba315b5f1..881917a4c94 100644
--- a/llvm/test/CodeGen/BPF/load.ll
+++ b/llvm/test/CodeGen/BPF/load.ll
@@ -5,7 +5,7 @@ define i16 @am1(i16* %a) nounwind {
ret i16 %1
}
; CHECK-LABEL: am1:
-; CHECK: ldh r0, 0(r1)
+; CHECK: r0 = *(u16 *)(r1 + 0)
@foo = external global i16
@@ -14,15 +14,15 @@ define i16 @am2() nounwind {
ret i16 %1
}
; CHECK-LABEL: am2:
-; CHECK: ldh r0, 0(r1)
+; CHECK: r0 = *(u16 *)(r1 + 0)
define i16 @am4() nounwind {
%1 = load volatile i16, i16* inttoptr(i16 32 to i16*)
ret i16 %1
}
; CHECK-LABEL: am4:
-; CHECK: mov r1, 32
-; CHECK: ldh r0, 0(r1)
+; CHECK: r1 = 32
+; CHECK: r0 = *(u16 *)(r1 + 0)
define i16 @am5(i16* %a) nounwind {
%1 = getelementptr i16, i16* %a, i16 2
@@ -30,7 +30,7 @@ define i16 @am5(i16* %a) nounwind {
ret i16 %2
}
; CHECK-LABEL: am5:
-; CHECK: ldh r0, 4(r1)
+; CHECK: r0 = *(u16 *)(r1 + 4)
%S = type { i16, i16 }
@baz = common global %S zeroinitializer, align 1
@@ -40,4 +40,4 @@ define i16 @am6() nounwind {
ret i16 %1
}
; CHECK-LABEL: am6:
-; CHECK: ldh r0, 2(r1)
+; CHECK: r0 = *(u16 *)(r1 + 2)
diff --git a/llvm/test/CodeGen/BPF/loops.ll b/llvm/test/CodeGen/BPF/loops.ll
index 00be54b3bac..39278fe595c 100644
--- a/llvm/test/CodeGen/BPF/loops.ll
+++ b/llvm/test/CodeGen/BPF/loops.ll
@@ -10,7 +10,7 @@ for.body: ; preds = %for.body, %entry
%sum.09 = phi i16 [ 0, %entry ], [ %add, %for.body ] ; <i16> [#uses=1]
%arrayidx = getelementptr i16, i16* %a, i16 %i.010 ; <i16*> [#uses=1]
; CHECK-LABEL: add:
-; CHECK: add r{{[0-9]+}}, r{{[0-9]+}}
+; CHECK: r{{[0-9]+}} += r{{[0-9]+}}
%tmp4 = load i16, i16* %arrayidx ; <i16> [#uses=1]
%add = add i16 %tmp4, %sum.09 ; <i16> [#uses=2]
%inc = add i16 %i.010, 1 ; <i16> [#uses=2]
@@ -32,7 +32,7 @@ for.body: ; preds = %for.body, %entry
%sum.09 = phi i16 [ 0, %entry ], [ %add, %for.body ] ; <i16> [#uses=1]
%arrayidx = getelementptr i16, i16* %a, i16 %i.010 ; <i16*> [#uses=1]
; CHECK-LABEL: sub:
-; CHECK: sub r{{[0-9]+}}, r{{[0-9]+}}
+; CHECK: r{{[0-9]+}} -= r{{[0-9]+}}
%tmp4 = load i16, i16* %arrayidx ; <i16> [#uses=1]
%add = sub i16 %tmp4, %sum.09 ; <i16> [#uses=2]
%inc = add i16 %i.010, 1 ; <i16> [#uses=2]
@@ -54,7 +54,7 @@ for.body: ; preds = %for.body, %entry
%sum.09 = phi i16 [ 0, %entry ], [ %add, %for.body ] ; <i16> [#uses=1]
%arrayidx = getelementptr i16, i16* %a, i16 %i.010 ; <i16*> [#uses=1]
; CHECK-LABEL: or:
-; CHECK: or r{{[0-9]+}}, r{{[0-9]+}}
+; CHECK: r{{[0-9]+}} |= r{{[0-9]+}}
%tmp4 = load i16, i16* %arrayidx ; <i16> [#uses=1]
%add = or i16 %tmp4, %sum.09 ; <i16> [#uses=2]
%inc = add i16 %i.010, 1 ; <i16> [#uses=2]
@@ -76,7 +76,7 @@ for.body: ; preds = %for.body, %entry
%sum.09 = phi i16 [ 0, %entry ], [ %add, %for.body ] ; <i16> [#uses=1]
%arrayidx = getelementptr i16, i16* %a, i16 %i.010 ; <i16*> [#uses=1]
; CHECK-LABEL: xor:
-; CHECK: xor r{{[0-9]+}}, r{{[0-9]+}}
+; CHECK: r{{[0-9]+}} ^= r{{[0-9]+}}
%tmp4 = load i16, i16* %arrayidx ; <i16> [#uses=1]
%add = xor i16 %tmp4, %sum.09 ; <i16> [#uses=2]
%inc = add i16 %i.010, 1 ; <i16> [#uses=2]
@@ -98,7 +98,7 @@ for.body: ; preds = %for.body, %entry
%sum.09 = phi i16 [ 0, %entry ], [ %add, %for.body ] ; <i16> [#uses=1]
%arrayidx = getelementptr i16, i16* %a, i16 %i.010 ; <i16*> [#uses=1]
; CHECK-LABEL: and:
-; CHECK: and r{{[0-9]+}}, r{{[0-9]+}}
+; CHECK: r{{[0-9]+}} &= r{{[0-9]+}}
%tmp4 = load i16, i16* %arrayidx ; <i16> [#uses=1]
%add = and i16 %tmp4, %sum.09 ; <i16> [#uses=2]
%inc = add i16 %i.010, 1 ; <i16> [#uses=2]
diff --git a/llvm/test/CodeGen/BPF/sanity.ll b/llvm/test/CodeGen/BPF/sanity.ll
index 7f0ef889ff9..f318c3a95e4 100644
--- a/llvm/test/CodeGen/BPF/sanity.ll
+++ b/llvm/test/CodeGen/BPF/sanity.ll
@@ -7,7 +7,7 @@ define i32 @foo_int(i32 %a, i32 %b) #0 {
%1 = add nsw i32 %b, %a
ret i32 %1
; CHECK-LABEL: foo_int:
-; CHECK: add r2, r1
+; CHECK: r2 += r1
}
; Function Attrs: nounwind readnone uwtable
@@ -15,9 +15,9 @@ define signext i8 @foo_char(i8 signext %a, i8 signext %b) #0 {
%1 = add i8 %b, %a
ret i8 %1
; CHECK-LABEL: foo_char:
-; CHECK: add r2, r1
-; CHECK: slli r2, 56
-; CHECK: srai r2, 56
+; CHECK: r2 += r1
+; CHECK: r2 <<= 56
+; CHECK: r2 s>>= 56
}
; Function Attrs: nounwind readnone uwtable
@@ -26,9 +26,9 @@ define i64 @foo_ll(i64 %a, i64 %b, i64 %c) #0 {
%2 = sub i64 %1, %c
ret i64 %2
; CHECK-LABEL: foo_ll:
-; CHECK: add r2, r1
-; CHECK: sub r2, r3
-; CHECK: mov r0, r2
+; CHECK: r2 += r1
+; CHECK: r2 -= r3
+; CHECK: r0 = r2
}
; Function Attrs: nounwind uwtable
@@ -37,9 +37,9 @@ define void @foo_call2(i32 %a, i32 %b) #1 {
tail call void @foo_2arg(i8 signext %1, i32 %a) #3
ret void
; CHECK-LABEL: foo_call2:
-; CHECK: slli r2, 56
-; CHECK: srai r2, 56
-; CHECK: mov r1, r2
+; CHECK: r2 <<= 56
+; CHECK: r2 s>>= 56
+; CHECK: r1 = r2
}
declare void @foo_2arg(i8 signext, i32) #2
@@ -60,7 +60,7 @@ define signext i8 @foo_cmp(i8 signext %a, i8 signext %b) #0 {
%a.b = select i1 %1, i8 %a, i8 %b
ret i8 %a.b
; CHECK-LABEL: foo_cmp:
-; CHECK: jsgt r2, r1
+; CHECK: if r2 s> r1
}
; Function Attrs: nounwind readnone uwtable
@@ -82,7 +82,7 @@ define i32 @foo_muldiv(i8 signext %a, i16 signext %b, i32 %c, i64 %d) #0 {
%.0 = phi i32 [ %4, %2 ], [ %7, %5 ]
ret i32 %.0
; CHECK-LABEL: foo_muldiv:
-; CHECK: mul r2, r3
+; CHECK: r2 *= r3
}
; Function Attrs: nounwind uwtable
@@ -90,11 +90,11 @@ define i32 @foo_optimized() #1 {
%1 = tail call i32 @manyarg(i32 1, i32 2, i32 3, i32 4, i32 5) #3
ret i32 %1
; CHECK-LABEL: foo_optimized:
-; CHECK: mov r1, 1
-; CHECK: mov r2, 2
-; CHECK: mov r3, 3
-; CHECK: mov r4, 4
-; CHECK: mov r5, 5
+; CHECK: r1 = 1
+; CHECK: r2 = 2
+; CHECK: r3 = 3
+; CHECK: r4 = 4
+; CHECK: r5 = 5
}
declare i32 @manyarg(i32, i32, i32, i32, i32) #2
@@ -105,7 +105,7 @@ define void @foo_printf() #1 {
%1 = getelementptr inbounds [9 x i8], [9 x i8]* %fmt, i64 0, i64 0
call void @llvm.memcpy.p0i8.p0i8.i64(i8* %1, i8* getelementptr inbounds ([9 x i8], [9 x i8]* @foo_printf.fmt, i64 0, i64 0), i64 9, i32 1, i1 false)
; CHECK-LABEL: foo_printf:
-; CHECK: ld_64 r1, 729618802566522216
+; CHECK: r1 = 729618802566522216ll
%2 = call i32 (i8*, ...) @printf(i8* %1) #3
ret void
}
diff --git a/llvm/test/CodeGen/BPF/setcc.ll b/llvm/test/CodeGen/BPF/setcc.ll
index f6c6db6c683..294c4936567 100644
--- a/llvm/test/CodeGen/BPF/setcc.ll
+++ b/llvm/test/CodeGen/BPF/setcc.ll
@@ -7,7 +7,7 @@ define i16 @sccweqand(i16 %a, i16 %b) nounwind {
ret i16 %t3
}
; CHECK-LABEL: sccweqand:
-; CHECK: jeq r1, r2
+; CHECK: if r1 == r2
define i16 @sccwneand(i16 %a, i16 %b) nounwind {
%t1 = and i16 %a, %b
@@ -16,7 +16,7 @@ define i16 @sccwneand(i16 %a, i16 %b) nounwind {
ret i16 %t3
}
; CHECK-LABEL: sccwneand:
-; CHECK: jne r1, r2
+; CHECK: if r1 != r2
define i16 @sccwne(i16 %a, i16 %b) nounwind {
%t1 = icmp ne i16 %a, %b
@@ -24,7 +24,7 @@ define i16 @sccwne(i16 %a, i16 %b) nounwind {
ret i16 %t2
}
; CHECK-LABEL:sccwne:
-; CHECK: jne r1, r2
+; CHECK: if r1 != r2
define i16 @sccweq(i16 %a, i16 %b) nounwind {
%t1 = icmp eq i16 %a, %b
@@ -32,7 +32,7 @@ define i16 @sccweq(i16 %a, i16 %b) nounwind {
ret i16 %t2
}
; CHECK-LABEL:sccweq:
-; CHECK: jeq r1, r2
+; CHECK: if r1 == r2
define i16 @sccwugt(i16 %a, i16 %b) nounwind {
%t1 = icmp ugt i16 %a, %b
@@ -40,7 +40,7 @@ define i16 @sccwugt(i16 %a, i16 %b) nounwind {
ret i16 %t2
}
; CHECK-LABEL:sccwugt:
-; CHECK: jgt r1, r2
+; CHECK: if r1 > r2
define i16 @sccwuge(i16 %a, i16 %b) nounwind {
%t1 = icmp uge i16 %a, %b
@@ -48,7 +48,7 @@ define i16 @sccwuge(i16 %a, i16 %b) nounwind {
ret i16 %t2
}
; CHECK-LABEL:sccwuge:
-; CHECK: jge r1, r2
+; CHECK: if r1 >= r2
define i16 @sccwult(i16 %a, i16 %b) nounwind {
%t1 = icmp ult i16 %a, %b
@@ -56,7 +56,7 @@ define i16 @sccwult(i16 %a, i16 %b) nounwind {
ret i16 %t2
}
; CHECK-LABEL:sccwult:
-; CHECK: jgt r2, r1
+; CHECK: if r2 > r1
define i16 @sccwule(i16 %a, i16 %b) nounwind {
%t1 = icmp ule i16 %a, %b
@@ -64,7 +64,7 @@ define i16 @sccwule(i16 %a, i16 %b) nounwind {
ret i16 %t2
}
; CHECK-LABEL:sccwule:
-; CHECK: jge r2, r1
+; CHECK: if r2 >= r1
define i16 @sccwsgt(i16 %a, i16 %b) nounwind {
%t1 = icmp sgt i16 %a, %b
@@ -72,7 +72,7 @@ define i16 @sccwsgt(i16 %a, i16 %b) nounwind {
ret i16 %t2
}
; CHECK-LABEL:sccwsgt:
-; CHECK: jsgt r1, r2
+; CHECK: if r1 s> r2
define i16 @sccwsge(i16 %a, i16 %b) nounwind {
%t1 = icmp sge i16 %a, %b
@@ -80,7 +80,7 @@ define i16 @sccwsge(i16 %a, i16 %b) nounwind {
ret i16 %t2
}
; CHECK-LABEL:sccwsge:
-; CHECK: jsge r1, r2
+; CHECK: if r1 s>= r2
define i16 @sccwslt(i16 %a, i16 %b) nounwind {
%t1 = icmp slt i16 %a, %b
@@ -88,7 +88,7 @@ define i16 @sccwslt(i16 %a, i16 %b) nounwind {
ret i16 %t2
}
; CHECK-LABEL:sccwslt:
-; CHECK: jsgt r2, r1
+; CHECK: if r2 s> r1
define i16 @sccwsle(i16 %a, i16 %b) nounwind {
%t1 = icmp sle i16 %a, %b
@@ -96,4 +96,4 @@ define i16 @sccwsle(i16 %a, i16 %b) nounwind {
ret i16 %t2
}
; CHECK-LABEL:sccwsle:
-; CHECK: jsge r2, r1
+; CHECK: if r2 s>= r1
diff --git a/llvm/test/CodeGen/BPF/shifts.ll b/llvm/test/CodeGen/BPF/shifts.ll
index cb000b92fcd..15e228c492d 100644
--- a/llvm/test/CodeGen/BPF/shifts.ll
+++ b/llvm/test/CodeGen/BPF/shifts.ll
@@ -3,7 +3,7 @@
define zeroext i8 @lshr8(i8 zeroext %a, i8 zeroext %cnt) nounwind readnone {
entry:
; CHECK-LABEL: lshr8:
-; CHECK: srl r1, r2 # encoding: [0x7f,0x21,0x00,0x00,0x00,0x00,0x00,0x00]
+; CHECK: r1 >>= r2 # encoding: [0x7f,0x21,0x00,0x00,0x00,0x00,0x00,0x00]
%shr = lshr i8 %a, %cnt
ret i8 %shr
}
@@ -11,7 +11,7 @@ entry:
define signext i8 @ashr8(i8 signext %a, i8 zeroext %cnt) nounwind readnone {
entry:
; CHECK-LABEL: ashr8:
-; CHECK: sra r1, r2 # encoding: [0xcf,0x21,0x00,0x00,0x00,0x00,0x00,0x00]
+; CHECK: r1 s>>= r2 # encoding: [0xcf,0x21,0x00,0x00,0x00,0x00,0x00,0x00]
%shr = ashr i8 %a, %cnt
ret i8 %shr
}
@@ -19,7 +19,7 @@ entry:
define zeroext i8 @shl8(i8 zeroext %a, i8 zeroext %cnt) nounwind readnone {
entry:
; CHECK: shl8
-; CHECK: sll r1, r2 # encoding: [0x6f,0x21,0x00,0x00,0x00,0x00,0x00,0x00]
+; CHECK: r1 <<= r2 # encoding: [0x6f,0x21,0x00,0x00,0x00,0x00,0x00,0x00]
%shl = shl i8 %a, %cnt
ret i8 %shl
}
@@ -27,7 +27,7 @@ entry:
define zeroext i16 @lshr16(i16 zeroext %a, i16 zeroext %cnt) nounwind readnone {
entry:
; CHECK-LABEL: lshr16:
-; CHECK: srl r1, r2 # encoding: [0x7f,0x21,0x00,0x00,0x00,0x00,0x00,0x00]
+; CHECK: r1 >>= r2 # encoding: [0x7f,0x21,0x00,0x00,0x00,0x00,0x00,0x00]
%shr = lshr i16 %a, %cnt
ret i16 %shr
}
@@ -35,7 +35,7 @@ entry:
define signext i16 @ashr16(i16 signext %a, i16 zeroext %cnt) nounwind readnone {
entry:
; CHECK-LABEL: ashr16:
-; CHECK: sra r1, r2 # encoding: [0xcf,0x21,0x00,0x00,0x00,0x00,0x00,0x00]
+; CHECK: r1 s>>= r2 # encoding: [0xcf,0x21,0x00,0x00,0x00,0x00,0x00,0x00]
%shr = ashr i16 %a, %cnt
ret i16 %shr
}
@@ -43,7 +43,7 @@ entry:
define zeroext i16 @shl16(i16 zeroext %a, i16 zeroext %cnt) nounwind readnone {
entry:
; CHECK-LABEL: shl16:
-; CHECK: sll r1, r2 # encoding: [0x6f,0x21,0x00,0x00,0x00,0x00,0x00,0x00]
+; CHECK: r1 <<= r2 # encoding: [0x6f,0x21,0x00,0x00,0x00,0x00,0x00,0x00]
%shl = shl i16 %a, %cnt
ret i16 %shl
}
@@ -51,8 +51,8 @@ entry:
define zeroext i32 @lshr32(i32 zeroext %a, i32 zeroext %cnt) nounwind readnone {
entry:
; CHECK-LABEL: lshr32:
-; CHECK: srl r1, r2 # encoding: [0x7f,0x21,0x00,0x00,0x00,0x00,0x00,0x00]
-; CHECK: slli r1, 32 # encoding: [0x67,0x01,0x00,0x00,0x20,0x00,0x00,0x00]
+; CHECK: r1 >>= r2 # encoding: [0x7f,0x21,0x00,0x00,0x00,0x00,0x00,0x00]
+; CHECK: r1 <<= 32 # encoding: [0x67,0x01,0x00,0x00,0x20,0x00,0x00,0x00]
%shr = lshr i32 %a, %cnt
ret i32 %shr
}
@@ -60,7 +60,7 @@ entry:
define signext i32 @ashr32(i32 signext %a, i32 zeroext %cnt) nounwind readnone {
entry:
; CHECK-LABEL: ashr32:
-; CHECK: sra r1, r2 # encoding: [0xcf,0x21,0x00,0x00,0x00,0x00,0x00,0x00]
+; CHECK: r1 s>>= r2 # encoding: [0xcf,0x21,0x00,0x00,0x00,0x00,0x00,0x00]
%shr = ashr i32 %a, %cnt
ret i32 %shr
}
@@ -68,7 +68,7 @@ entry:
define zeroext i32 @shl32(i32 zeroext %a, i32 zeroext %cnt) nounwind readnone {
entry:
; CHECK-LABEL: shl32:
-; CHECK: sll r1, r2 # encoding: [0x6f,0x21,0x00,0x00,0x00,0x00,0x00,0x00]
+; CHECK: r1 <<= r2 # encoding: [0x6f,0x21,0x00,0x00,0x00,0x00,0x00,0x00]
%shl = shl i32 %a, %cnt
ret i32 %shl
}
@@ -76,7 +76,7 @@ entry:
define zeroext i64 @lshr64(i64 zeroext %a, i64 zeroext %cnt) nounwind readnone {
entry:
; CHECK-LABEL: lshr64:
-; CHECK: srl r1, r2 # encoding: [0x7f,0x21,0x00,0x00,0x00,0x00,0x00,0x00]
+; CHECK: r1 >>= r2 # encoding: [0x7f,0x21,0x00,0x00,0x00,0x00,0x00,0x00]
%shr = lshr i64 %a, %cnt
ret i64 %shr
}
@@ -84,7 +84,7 @@ entry:
define signext i64 @ashr64(i64 signext %a, i64 zeroext %cnt) nounwind readnone {
entry:
; CHECK-LABEL: ashr64:
-; CHECK: sra r1, r2 # encoding: [0xcf,0x21,0x00,0x00,0x00,0x00,0x00,0x00]
+; CHECK: r1 s>>= r2 # encoding: [0xcf,0x21,0x00,0x00,0x00,0x00,0x00,0x00]
%shr = ashr i64 %a, %cnt
ret i64 %shr
}
@@ -92,9 +92,9 @@ entry:
define zeroext i64 @shl64(i64 zeroext %a, i64 zeroext %cnt) nounwind readnone {
entry:
; CHECK-LABEL: shl64:
-; CHECK: sll r1, r2 # encoding: [0x6f,0x21,0x00,0x00,0x00,0x00,0x00,0x00]
-; CHECK: mov r0, r1 # encoding: [0xbf,0x10,0x00,0x00,0x00,0x00,0x00,0x00]
-; CHECK: ret # encoding: [0x95,0x00,0x00,0x00,0x00,0x00,0x00,0x00]
+; CHECK: r1 <<= r2 # encoding: [0x6f,0x21,0x00,0x00,0x00,0x00,0x00,0x00]
+; CHECK: r0 = r1 # encoding: [0xbf,0x10,0x00,0x00,0x00,0x00,0x00,0x00]
+; CHECK: exit # encoding: [0x95,0x00,0x00,0x00,0x00,0x00,0x00,0x00]
%shl = shl i64 %a, %cnt
ret i64 %shl
}
diff --git a/llvm/test/CodeGen/BPF/sockex2.ll b/llvm/test/CodeGen/BPF/sockex2.ll
index b3e83eadf53..d5f070ea605 100644
--- a/llvm/test/CodeGen/BPF/sockex2.ll
+++ b/llvm/test/CodeGen/BPF/sockex2.ll
@@ -309,11 +309,10 @@ parse_ip.exit.i: ; preds = %39, %35, %33
flow_dissector.exit.thread: ; preds = %86, %12, %196, %199
ret i32 0
; CHECK-LABEL: bpf_prog2:
-; CHECK: ldabs_h r0, r6.data + 12 # encoding: [0x28,0x00,0x00,0x00,0x0c,0x00,0x00,0x00]
-; CHECK: ldabs_h r0, r6.data + 16 # encoding: [0x28,0x00,0x00,0x00,0x10,0x00,0x00,0x00]
+; CHECK: r0 = *(u16 *)skb[12] # encoding: [0x28,0x00,0x00,0x00,0x0c,0x00,0x00,0x00]
+; CHECK: r0 = *(u16 *)skb[16] # encoding: [0x28,0x00,0x00,0x00,0x10,0x00,0x00,0x00]
; CHECK: implicit-def: %R1
-; CHECK: ld_64 r1
-; CHECK-NOT: ori
+; CHECK: r1 =
; CHECK: call 1 # encoding: [0x85,0x00,0x00,0x00,0x01,0x00,0x00,0x00]
; CHECK: call 2 # encoding: [0x85,0x00,0x00,0x00,0x02,0x00,0x00,0x00]
}
diff --git a/llvm/test/CodeGen/BPF/undef.ll b/llvm/test/CodeGen/BPF/undef.ll
index ef712c4a595..1a925ccae80 100644
--- a/llvm/test/CodeGen/BPF/undef.ll
+++ b/llvm/test/CodeGen/BPF/undef.ll
@@ -15,48 +15,48 @@
define i32 @ebpf_filter(%struct.__sk_buff* nocapture readnone %ebpf_packet) #0 section "socket1" {
%key = alloca %struct.routing_key_2, align 1
%1 = getelementptr inbounds %struct.routing_key_2, %struct.routing_key_2* %key, i64 0, i32 0, i64 0
-; CHECK: mov r1, 5
-; CHECK: stb -8(r10), r1
+; CHECK: r1 = 5
+; CHECK: *(u8 *)(r10 - 8) = r1
store i8 5, i8* %1, align 1
%2 = getelementptr inbounds %struct.routing_key_2, %struct.routing_key_2* %key, i64 0, i32 0, i64 1
-; CHECK: mov r1, 6
-; CHECK: stb -7(r10), r1
+; CHECK: r1 = 6
+; CHECK: *(u8 *)(r10 - 7) = r1
store i8 6, i8* %2, align 1
%3 = getelementptr inbounds %struct.routing_key_2, %struct.routing_key_2* %key, i64 0, i32 0, i64 2
-; CHECK: mov r1, 7
-; CHECK: stb -6(r10), r1
+; CHECK: r1 = 7
+; CHECK: *(u8 *)(r10 - 6) = r1
store i8 7, i8* %3, align 1
%4 = getelementptr inbounds %struct.routing_key_2, %struct.routing_key_2* %key, i64 0, i32 0, i64 3
-; CHECK: mov r1, 8
-; CHECK: stb -5(r10), r1
+; CHECK: r1 = 8
+; CHECK: *(u8 *)(r10 - 5) = r1
store i8 8, i8* %4, align 1
%5 = getelementptr inbounds %struct.routing_key_2, %struct.routing_key_2* %key, i64 0, i32 0, i64 4
-; CHECK: mov r1, 9
-; CHECK: stb -4(r10), r1
+; CHECK: r1 = 9
+; CHECK: *(u8 *)(r10 - 4) = r1
store i8 9, i8* %5, align 1
%6 = getelementptr inbounds %struct.routing_key_2, %struct.routing_key_2* %key, i64 0, i32 0, i64 5
-; CHECK: mov r1, 10
-; CHECK: stb -3(r10), r1
+; CHECK: r1 = 10
+; CHECK: *(u8 *)(r10 - 3) = r1
store i8 10, i8* %6, align 1
%7 = getelementptr inbounds %struct.routing_key_2, %struct.routing_key_2* %key, i64 1, i32 0, i64 0
-; CHECK: mov r1, r10
-; CHECK: addi r1, -2
-; CHECK: mov r2, 0
-; CHECK: sth 6(r1), r2
-; CHECK: sth 4(r1), r2
-; CHECK: sth 2(r1), r2
-; CHECK: sth 24(r10), r2
-; CHECK: sth 22(r10), r2
-; CHECK: sth 20(r10), r2
-; CHECK: sth 18(r10), r2
-; CHECK: sth 16(r10), r2
-; CHECK: sth 14(r10), r2
-; CHECK: sth 12(r10), r2
-; CHECK: sth 10(r10), r2
-; CHECK: sth 8(r10), r2
-; CHECK: sth 6(r10), r2
-; CHECK: sth -2(r10), r2
-; CHECK: sth 26(r10), r2
+; CHECK: r1 = r10
+; CHECK: r1 += -2
+; CHECK: r2 = 0
+; CHECK: *(u16 *)(r1 + 6) = r2
+; CHECK: *(u16 *)(r1 + 4) = r2
+; CHECK: *(u16 *)(r1 + 2) = r2
+; CHECK: *(u16 *)(r10 + 24) = r2
+; CHECK: *(u16 *)(r10 + 22) = r2
+; CHECK: *(u16 *)(r10 + 20) = r2
+; CHECK: *(u16 *)(r10 + 18) = r2
+; CHECK: *(u16 *)(r10 + 16) = r2
+; CHECK: *(u16 *)(r10 + 14) = r2
+; CHECK: *(u16 *)(r10 + 12) = r2
+; CHECK: *(u16 *)(r10 + 10) = r2
+; CHECK: *(u16 *)(r10 + 8) = r2
+; CHECK: *(u16 *)(r10 + 6) = r2
+; CHECK: *(u16 *)(r10 - 2) = r2
+; CHECK: *(u16 *)(r10 + 26) = r2
call void @llvm.memset.p0i8.i64(i8* %7, i8 0, i64 30, i32 1, i1 false)
%8 = call i32 (%struct.bpf_map_def*, %struct.routing_key_2*, ...) bitcast (i32 (...)* @bpf_map_lookup_elem to i32 (%struct.bpf_map_def*, %struct.routing_key_2*, ...)*)(%struct.bpf_map_def* nonnull @routing, %struct.routing_key_2* nonnull %key) #3
ret i32 undef
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