diff options
| -rw-r--r-- | llvm/lib/Target/X86/AsmParser/X86AsmParser.cpp | 11 | ||||
| -rw-r--r-- | llvm/test/MC/AsmParser/X86/x86_64-new-encoder.s | 5 |
2 files changed, 16 insertions, 0 deletions
diff --git a/llvm/lib/Target/X86/AsmParser/X86AsmParser.cpp b/llvm/lib/Target/X86/AsmParser/X86AsmParser.cpp index cddf8ebfc07..58e4554ab03 100644 --- a/llvm/lib/Target/X86/AsmParser/X86AsmParser.cpp +++ b/llvm/lib/Target/X86/AsmParser/X86AsmParser.cpp @@ -753,6 +753,7 @@ ParseInstruction(StringRef Name, SMLoc NameLoc, PatchedName = "vpclmulqdq"; } } + Operands.push_back(X86Operand::CreateToken(PatchedName, NameLoc)); if (ExtraImmOp) @@ -827,6 +828,16 @@ ParseInstruction(StringRef Name, SMLoc NameLoc, delete Operands[0]; Operands[0] = X86Operand::CreateToken("sldtw", NameLoc); } + + // The assembler accepts "xchgX <reg>, <mem>" and "xchgX <mem>, <reg>" as + // synonyms. Our tables only have the "<reg>, <mem>" form, so if we see the + // other operand order, swap them. + if (Name == "xchgb" || Name == "xchgw" || Name == "xchgl" || Name == "xchgq") + if (Operands.size() == 3 && + static_cast<X86Operand*>(Operands[1])->isMem() && + static_cast<X86Operand*>(Operands[2])->isReg()) { + std::swap(Operands[1], Operands[2]); + } return false; } diff --git a/llvm/test/MC/AsmParser/X86/x86_64-new-encoder.s b/llvm/test/MC/AsmParser/X86/x86_64-new-encoder.s index 3644147b167..7992972c988 100644 --- a/llvm/test/MC/AsmParser/X86/x86_64-new-encoder.s +++ b/llvm/test/MC/AsmParser/X86/x86_64-new-encoder.s @@ -168,3 +168,8 @@ L1: // CHECK: jrcxz L1 // CHECK: encoding: [0xe3,A] +// PR8061 +xchgl 368(%rax),%ecx +// CHECK: xchgl %ecx, 368(%rax) +xchgl %ecx, 368(%rax) +// CHECK: xchgl %ecx, 368(%rax) |
