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-rw-r--r--llvm/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp70
-rw-r--r--llvm/test/CodeGen/AArch64/funnel-shift-rot.ll40
-rw-r--r--llvm/test/CodeGen/AArch64/funnel-shift.ll66
-rw-r--r--llvm/test/CodeGen/PowerPC/funnel-shift-rot.ll32
-rw-r--r--llvm/test/CodeGen/PowerPC/funnel-shift.ll32
-rw-r--r--llvm/test/CodeGen/X86/funnel-shift-rot.ll39
-rw-r--r--llvm/test/CodeGen/X86/funnel-shift.ll250
7 files changed, 217 insertions, 312 deletions
diff --git a/llvm/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp b/llvm/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp
index 5f6b6010cae..96ab438f996 100644
--- a/llvm/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp
+++ b/llvm/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp
@@ -5693,43 +5693,51 @@ SelectionDAGBuilder::visitIntrinsicCall(const CallInst &I, unsigned Intrinsic) {
SDValue Y = getValue(I.getArgOperand(1));
SDValue Z = getValue(I.getArgOperand(2));
EVT VT = X.getValueType();
+ SDValue BitWidthC = DAG.getConstant(VT.getScalarSizeInBits(), sdl, VT);
+ SDValue Zero = DAG.getConstant(0, sdl, VT);
+ SDValue ShAmt = DAG.getNode(ISD::UREM, sdl, VT, Z, BitWidthC);
- // When X == Y, this is rotate. Create the node directly if legal.
- // TODO: This should also be done if the operation is custom, but we have
- // to make sure targets are handling the modulo shift amount as expected.
- // TODO: If the rotate direction (left or right) corresponding to the shift
- // is not available, adjust the shift value and invert the direction.
- auto RotateOpcode = IsFSHL ? ISD::ROTL : ISD::ROTR;
- if (X == Y && TLI.isOperationLegal(RotateOpcode, VT)) {
- setValue(&I, DAG.getNode(RotateOpcode, sdl, VT, X, Z));
+ // When X == Y, this is rotate. If the data type has a power-of-2 size, we
+ // avoid the select that is necessary in the general case to filter out
+ // the 0-shift possibility that leads to UB.
+ if (X == Y && isPowerOf2_32(VT.getScalarSizeInBits())) {
+ // TODO: This should also be done if the operation is custom, but we have
+ // to make sure targets are handling the modulo shift amount as expected.
+ // TODO: If the rotate direction (left or right) corresponding to the
+ // shift is not available, adjust the shift value and invert the
+ // direction.
+ auto RotateOpcode = IsFSHL ? ISD::ROTL : ISD::ROTR;
+ if (TLI.isOperationLegal(RotateOpcode, VT)) {
+ setValue(&I, DAG.getNode(RotateOpcode, sdl, VT, X, Z));
+ return nullptr;
+ }
+ // fshl (rotl): (X << (Z % BW)) | (X >> ((0 - Z) % BW))
+ // fshr (rotr): (X << ((0 - Z) % BW)) | (X >> (Z % BW))
+ SDValue NegZ = DAG.getNode(ISD::SUB, sdl, VT, Zero, Z);
+ SDValue NShAmt = DAG.getNode(ISD::UREM, sdl, VT, NegZ, BitWidthC);
+ SDValue ShX = DAG.getNode(ISD::SHL, sdl, VT, X, IsFSHL ? ShAmt : NShAmt);
+ SDValue ShY = DAG.getNode(ISD::SRL, sdl, VT, X, IsFSHL ? NShAmt : ShAmt);
+ setValue(&I, DAG.getNode(ISD::OR, sdl, VT, ShX, ShY));
return nullptr;
}
- // Get the shift amount and inverse shift amount, modulo the bit-width.
- SDValue BitWidthC = DAG.getConstant(VT.getScalarSizeInBits(), sdl, VT);
- SDValue ShAmt = DAG.getNode(ISD::UREM, sdl, VT, Z, BitWidthC);
- SDValue NegZ = DAG.getNode(ISD::SUB, sdl, VT, BitWidthC, Z);
- SDValue InvShAmt = DAG.getNode(ISD::UREM, sdl, VT, NegZ, BitWidthC);
-
- // fshl: (X << (Z % BW)) | (Y >> ((BW - Z) % BW))
- // fshr: (X << ((BW - Z) % BW)) | (Y >> (Z % BW))
+ // fshl: (X << (Z % BW)) | (Y >> (BW - (Z % BW)))
+ // fshr: (X << (BW - (Z % BW))) | (Y >> (Z % BW))
+ SDValue InvShAmt = DAG.getNode(ISD::SUB, sdl, VT, BitWidthC, ShAmt);
SDValue ShX = DAG.getNode(ISD::SHL, sdl, VT, X, IsFSHL ? ShAmt : InvShAmt);
SDValue ShY = DAG.getNode(ISD::SRL, sdl, VT, Y, IsFSHL ? InvShAmt : ShAmt);
- SDValue Res = DAG.getNode(ISD::OR, sdl, VT, ShX, ShY);
-
- // If (Z % BW == 0), then (BW - Z) % BW is also zero, so the result would
- // be X | Y. If X == Y (rotate), that's fine. If not, we have to select.
- if (X != Y) {
- SDValue Zero = DAG.getConstant(0, sdl, VT);
- EVT CCVT = MVT::i1;
- if (VT.isVector())
- CCVT = EVT::getVectorVT(*Context, CCVT, VT.getVectorNumElements());
- // For fshl, 0 shift returns the 1st arg (X).
- // For fshr, 0 shift returns the 2nd arg (Y).
- SDValue IsZeroShift = DAG.getSetCC(sdl, CCVT, ShAmt, Zero, ISD::SETEQ);
- Res = DAG.getSelect(sdl, VT, IsZeroShift, IsFSHL ? X : Y, Res);
- }
- setValue(&I, Res);
+ SDValue Or = DAG.getNode(ISD::OR, sdl, VT, ShX, ShY);
+
+ // If (Z % BW == 0), then the opposite direction shift is shift-by-bitwidth,
+ // and that is undefined. We must compare and select to avoid UB.
+ EVT CCVT = MVT::i1;
+ if (VT.isVector())
+ CCVT = EVT::getVectorVT(*Context, CCVT, VT.getVectorNumElements());
+
+ // For fshl, 0-shift returns the 1st arg (X).
+ // For fshr, 0-shift returns the 2nd arg (Y).
+ SDValue IsZeroShift = DAG.getSetCC(sdl, CCVT, ShAmt, Zero, ISD::SETEQ);
+ setValue(&I, DAG.getSelect(sdl, VT, IsZeroShift, IsFSHL ? X : Y, Or));
return nullptr;
}
case Intrinsic::stacksave: {
diff --git a/llvm/test/CodeGen/AArch64/funnel-shift-rot.ll b/llvm/test/CodeGen/AArch64/funnel-shift-rot.ll
index af612eafd33..9062c86924d 100644
--- a/llvm/test/CodeGen/AArch64/funnel-shift-rot.ll
+++ b/llvm/test/CodeGen/AArch64/funnel-shift-rot.ll
@@ -40,8 +40,7 @@ define i64 @rotl_i64_const_shift(i64 %x) {
define i16 @rotl_i16(i16 %x, i16 %z) {
; CHECK-LABEL: rotl_i16:
; CHECK: // %bb.0:
-; CHECK-NEXT: orr w10, wzr, #0x10
-; CHECK-NEXT: sub w10, w10, w1
+; CHECK-NEXT: neg w10, w1
; CHECK-NEXT: and w8, w0, #0xffff
; CHECK-NEXT: and w9, w1, #0xf
; CHECK-NEXT: and w10, w10, #0xf
@@ -56,8 +55,7 @@ define i16 @rotl_i16(i16 %x, i16 %z) {
define i32 @rotl_i32(i32 %x, i32 %z) {
; CHECK-LABEL: rotl_i32:
; CHECK: // %bb.0:
-; CHECK-NEXT: orr w8, wzr, #0x20
-; CHECK-NEXT: sub w8, w8, w1
+; CHECK-NEXT: neg w8, w1
; CHECK-NEXT: ror w0, w0, w8
; CHECK-NEXT: ret
%f = call i32 @llvm.fshl.i32(i32 %x, i32 %x, i32 %z)
@@ -67,8 +65,7 @@ define i32 @rotl_i32(i32 %x, i32 %z) {
define i64 @rotl_i64(i64 %x, i64 %z) {
; CHECK-LABEL: rotl_i64:
; CHECK: // %bb.0:
-; CHECK-NEXT: orr w9, wzr, #0x40
-; CHECK-NEXT: sub w9, w9, w1
+; CHECK-NEXT: neg w9, w1
; CHECK-NEXT: lsl x8, x0, x1
; CHECK-NEXT: lsr x9, x0, x9
; CHECK-NEXT: orr x0, x8, x9
@@ -83,14 +80,13 @@ define <4 x i32> @rotl_v4i32(<4 x i32> %x, <4 x i32> %z) {
; CHECK-LABEL: rotl_v4i32:
; CHECK: // %bb.0:
; CHECK-NEXT: movi v2.4s, #31
-; CHECK-NEXT: movi v3.4s, #32
-; CHECK-NEXT: and v4.16b, v1.16b, v2.16b
-; CHECK-NEXT: sub v1.4s, v3.4s, v1.4s
+; CHECK-NEXT: neg v3.4s, v1.4s
; CHECK-NEXT: and v1.16b, v1.16b, v2.16b
-; CHECK-NEXT: neg v1.4s, v1.4s
-; CHECK-NEXT: ushl v3.4s, v0.4s, v4.4s
-; CHECK-NEXT: ushl v0.4s, v0.4s, v1.4s
-; CHECK-NEXT: orr v0.16b, v3.16b, v0.16b
+; CHECK-NEXT: and v2.16b, v3.16b, v2.16b
+; CHECK-NEXT: neg v2.4s, v2.4s
+; CHECK-NEXT: ushl v1.4s, v0.4s, v1.4s
+; CHECK-NEXT: ushl v0.4s, v0.4s, v2.4s
+; CHECK-NEXT: orr v0.16b, v1.16b, v0.16b
; CHECK-NEXT: ret
%f = call <4 x i32> @llvm.fshl.v4i32(<4 x i32> %x, <4 x i32> %x, <4 x i32> %z)
ret <4 x i32> %f
@@ -140,10 +136,9 @@ define i16 @rotr_i16(i16 %x, i16 %z) {
; CHECK: // %bb.0:
; CHECK-NEXT: and w8, w0, #0xffff
; CHECK-NEXT: and w9, w1, #0xf
-; CHECK-NEXT: orr w10, wzr, #0x10
+; CHECK-NEXT: neg w10, w1
; CHECK-NEXT: lsr w8, w8, w9
-; CHECK-NEXT: sub w9, w10, w1
-; CHECK-NEXT: and w9, w9, #0xf
+; CHECK-NEXT: and w9, w10, #0xf
; CHECK-NEXT: lsl w9, w0, w9
; CHECK-NEXT: orr w0, w9, w8
; CHECK-NEXT: ret
@@ -175,14 +170,13 @@ define <4 x i32> @rotr_v4i32(<4 x i32> %x, <4 x i32> %z) {
; CHECK-LABEL: rotr_v4i32:
; CHECK: // %bb.0:
; CHECK-NEXT: movi v2.4s, #31
-; CHECK-NEXT: movi v3.4s, #32
-; CHECK-NEXT: and v4.16b, v1.16b, v2.16b
-; CHECK-NEXT: sub v1.4s, v3.4s, v1.4s
-; CHECK-NEXT: neg v3.4s, v4.4s
+; CHECK-NEXT: neg v3.4s, v1.4s
; CHECK-NEXT: and v1.16b, v1.16b, v2.16b
-; CHECK-NEXT: ushl v2.4s, v0.4s, v3.4s
-; CHECK-NEXT: ushl v0.4s, v0.4s, v1.4s
-; CHECK-NEXT: orr v0.16b, v0.16b, v2.16b
+; CHECK-NEXT: and v2.16b, v3.16b, v2.16b
+; CHECK-NEXT: neg v1.4s, v1.4s
+; CHECK-NEXT: ushl v1.4s, v0.4s, v1.4s
+; CHECK-NEXT: ushl v0.4s, v0.4s, v2.4s
+; CHECK-NEXT: orr v0.16b, v0.16b, v1.16b
; CHECK-NEXT: ret
%f = call <4 x i32> @llvm.fshr.v4i32(<4 x i32> %x, <4 x i32> %x, <4 x i32> %z)
ret <4 x i32> %f
diff --git a/llvm/test/CodeGen/AArch64/funnel-shift.ll b/llvm/test/CodeGen/AArch64/funnel-shift.ll
index d91a9c54cef..a1fac70545c 100644
--- a/llvm/test/CodeGen/AArch64/funnel-shift.ll
+++ b/llvm/test/CodeGen/AArch64/funnel-shift.ll
@@ -18,8 +18,8 @@ declare <4 x i32> @llvm.fshr.v4i32(<4 x i32>, <4 x i32>, <4 x i32>)
define i32 @fshl_i32(i32 %x, i32 %y, i32 %z) {
; CHECK-LABEL: fshl_i32:
; CHECK: // %bb.0:
-; CHECK-NEXT: orr w9, wzr, #0x20
-; CHECK-NEXT: sub w9, w9, w2
+; CHECK-NEXT: and w9, w2, #0x1f
+; CHECK-NEXT: neg w9, w9
; CHECK-NEXT: lsl w8, w0, w2
; CHECK-NEXT: lsr w9, w1, w9
; CHECK-NEXT: orr w8, w8, w9
@@ -35,26 +35,22 @@ declare i37 @llvm.fshl.i37(i37, i37, i37)
define i37 @fshl_i37(i37 %x, i37 %y, i37 %z) {
; CHECK-LABEL: fshl_i37:
; CHECK: // %bb.0:
-; CHECK-NEXT: mov x11, #31883
-; CHECK-NEXT: mov w10, #37
-; CHECK-NEXT: movk x11, #3542, lsl #16
-; CHECK-NEXT: movk x11, #51366, lsl #32
-; CHECK-NEXT: sub x12, x10, x2
-; CHECK-NEXT: and x8, x2, #0x1fffffffff
-; CHECK-NEXT: movk x11, #56679, lsl #48
-; CHECK-NEXT: and x12, x12, #0x1fffffffff
-; CHECK-NEXT: umulh x13, x8, x11
-; CHECK-NEXT: umulh x11, x12, x11
-; CHECK-NEXT: lsr x13, x13, #5
-; CHECK-NEXT: lsr x11, x11, #5
-; CHECK-NEXT: and x9, x1, #0x1fffffffff
-; CHECK-NEXT: msub x8, x13, x10, x8
-; CHECK-NEXT: msub x10, x11, x10, x12
-; CHECK-NEXT: lsl x13, x0, x8
-; CHECK-NEXT: lsr x9, x9, x10
-; CHECK-NEXT: orr x9, x13, x9
-; CHECK-NEXT: cmp x8, #0 // =0
-; CHECK-NEXT: csel x0, x0, x9, eq
+; CHECK-NEXT: mov x10, #31883
+; CHECK-NEXT: movk x10, #3542, lsl #16
+; CHECK-NEXT: movk x10, #51366, lsl #32
+; CHECK-NEXT: and x9, x2, #0x1fffffffff
+; CHECK-NEXT: movk x10, #56679, lsl #48
+; CHECK-NEXT: umulh x10, x9, x10
+; CHECK-NEXT: mov w11, #37
+; CHECK-NEXT: lsr x10, x10, #5
+; CHECK-NEXT: msub x9, x10, x11, x9
+; CHECK-NEXT: and x8, x1, #0x1fffffffff
+; CHECK-NEXT: sub x11, x11, x9
+; CHECK-NEXT: lsl x10, x0, x9
+; CHECK-NEXT: lsr x8, x8, x11
+; CHECK-NEXT: orr x8, x10, x8
+; CHECK-NEXT: cmp x9, #0 // =0
+; CHECK-NEXT: csel x0, x0, x8, eq
; CHECK-NEXT: ret
%f = call i37 @llvm.fshl.i37(i37 %x, i37 %y, i37 %z)
ret i37 %f
@@ -150,8 +146,8 @@ define i8 @fshl_i8_const_fold() {
define i32 @fshr_i32(i32 %x, i32 %y, i32 %z) {
; CHECK-LABEL: fshr_i32:
; CHECK: // %bb.0:
-; CHECK-NEXT: orr w9, wzr, #0x20
-; CHECK-NEXT: sub w9, w9, w2
+; CHECK-NEXT: and w9, w2, #0x1f
+; CHECK-NEXT: neg w9, w9
; CHECK-NEXT: lsr w8, w1, w2
; CHECK-NEXT: lsl w9, w0, w9
; CHECK-NEXT: orr w8, w9, w8
@@ -167,21 +163,17 @@ declare i37 @llvm.fshr.i37(i37, i37, i37)
define i37 @fshr_i37(i37 %x, i37 %y, i37 %z) {
; CHECK-LABEL: fshr_i37:
; CHECK: // %bb.0:
-; CHECK-NEXT: mov x11, #31883
-; CHECK-NEXT: mov w10, #37
-; CHECK-NEXT: movk x11, #3542, lsl #16
-; CHECK-NEXT: movk x11, #51366, lsl #32
-; CHECK-NEXT: sub x12, x10, x2
+; CHECK-NEXT: mov x10, #31883
+; CHECK-NEXT: movk x10, #3542, lsl #16
+; CHECK-NEXT: movk x10, #51366, lsl #32
; CHECK-NEXT: and x9, x2, #0x1fffffffff
-; CHECK-NEXT: movk x11, #56679, lsl #48
-; CHECK-NEXT: and x12, x12, #0x1fffffffff
-; CHECK-NEXT: umulh x13, x9, x11
-; CHECK-NEXT: umulh x11, x12, x11
-; CHECK-NEXT: lsr x13, x13, #5
-; CHECK-NEXT: lsr x11, x11, #5
+; CHECK-NEXT: movk x10, #56679, lsl #48
+; CHECK-NEXT: umulh x10, x9, x10
+; CHECK-NEXT: mov w11, #37
+; CHECK-NEXT: lsr x10, x10, #5
+; CHECK-NEXT: msub x9, x10, x11, x9
; CHECK-NEXT: and x8, x1, #0x1fffffffff
-; CHECK-NEXT: msub x9, x13, x10, x9
-; CHECK-NEXT: msub x10, x11, x10, x12
+; CHECK-NEXT: sub x10, x11, x9
; CHECK-NEXT: lsr x8, x8, x9
; CHECK-NEXT: lsl x10, x0, x10
; CHECK-NEXT: orr x8, x10, x8
diff --git a/llvm/test/CodeGen/PowerPC/funnel-shift-rot.ll b/llvm/test/CodeGen/PowerPC/funnel-shift-rot.ll
index d93c9361b35..35f46e7154b 100644
--- a/llvm/test/CodeGen/PowerPC/funnel-shift-rot.ll
+++ b/llvm/test/CodeGen/PowerPC/funnel-shift-rot.ll
@@ -40,7 +40,7 @@ define i64 @rotl_i64_const_shift(i64 %x) {
define i16 @rotl_i16(i16 %x, i16 %z) {
; CHECK-LABEL: rotl_i16:
; CHECK: # %bb.0:
-; CHECK-NEXT: subfic 5, 4, 16
+; CHECK-NEXT: neg 5, 4
; CHECK-NEXT: clrlwi 6, 3, 16
; CHECK-NEXT: rlwinm 4, 4, 0, 28, 31
; CHECK-NEXT: clrlwi 5, 5, 28
@@ -75,13 +75,11 @@ define i64 @rotl_i64(i64 %x, i64 %z) {
define <4 x i32> @rotl_v4i32(<4 x i32> %x, <4 x i32> %z) {
; CHECK-LABEL: rotl_v4i32:
; CHECK: # %bb.0:
-; CHECK-NEXT: addis 3, 2, .LCPI5_0@toc@ha
-; CHECK-NEXT: addi 3, 3, .LCPI5_0@toc@l
-; CHECK-NEXT: lvx 4, 0, 3
-; CHECK-NEXT: vsubuwm 4, 4, 3
-; CHECK-NEXT: vslw 3, 2, 3
-; CHECK-NEXT: vsrw 2, 2, 4
-; CHECK-NEXT: xxlor 34, 35, 34
+; CHECK-NEXT: xxlxor 36, 36, 36
+; CHECK-NEXT: vslw 5, 2, 3
+; CHECK-NEXT: vsubuwm 3, 4, 3
+; CHECK-NEXT: vsrw 2, 2, 3
+; CHECK-NEXT: xxlor 34, 37, 34
; CHECK-NEXT: blr
%f = call <4 x i32> @llvm.fshl.v4i32(<4 x i32> %x, <4 x i32> %x, <4 x i32> %z)
ret <4 x i32> %f
@@ -131,7 +129,7 @@ define i32 @rotr_i32_const_shift(i32 %x) {
define i16 @rotr_i16(i16 %x, i16 %z) {
; CHECK-LABEL: rotr_i16:
; CHECK: # %bb.0:
-; CHECK-NEXT: subfic 5, 4, 16
+; CHECK-NEXT: neg 5, 4
; CHECK-NEXT: clrlwi 6, 3, 16
; CHECK-NEXT: rlwinm 4, 4, 0, 28, 31
; CHECK-NEXT: clrlwi 5, 5, 28
@@ -146,7 +144,7 @@ define i16 @rotr_i16(i16 %x, i16 %z) {
define i32 @rotr_i32(i32 %x, i32 %z) {
; CHECK-LABEL: rotr_i32:
; CHECK: # %bb.0:
-; CHECK-NEXT: subfic 4, 4, 32
+; CHECK-NEXT: neg 4, 4
; CHECK-NEXT: clrlwi 4, 4, 27
; CHECK-NEXT: rlwnm 3, 3, 4, 0, 31
; CHECK-NEXT: blr
@@ -157,7 +155,7 @@ define i32 @rotr_i32(i32 %x, i32 %z) {
define i64 @rotr_i64(i64 %x, i64 %z) {
; CHECK-LABEL: rotr_i64:
; CHECK: # %bb.0:
-; CHECK-NEXT: subfic 4, 4, 64
+; CHECK-NEXT: neg 4, 4
; CHECK-NEXT: rlwinm 4, 4, 0, 26, 31
; CHECK-NEXT: rotld 3, 3, 4
; CHECK-NEXT: blr
@@ -170,13 +168,11 @@ define i64 @rotr_i64(i64 %x, i64 %z) {
define <4 x i32> @rotr_v4i32(<4 x i32> %x, <4 x i32> %z) {
; CHECK-LABEL: rotr_v4i32:
; CHECK: # %bb.0:
-; CHECK-NEXT: addis 3, 2, .LCPI12_0@toc@ha
-; CHECK-NEXT: addi 3, 3, .LCPI12_0@toc@l
-; CHECK-NEXT: lvx 4, 0, 3
-; CHECK-NEXT: vsubuwm 4, 4, 3
-; CHECK-NEXT: vsrw 3, 2, 3
-; CHECK-NEXT: vslw 2, 2, 4
-; CHECK-NEXT: xxlor 34, 34, 35
+; CHECK-NEXT: xxlxor 36, 36, 36
+; CHECK-NEXT: vsrw 5, 2, 3
+; CHECK-NEXT: vsubuwm 3, 4, 3
+; CHECK-NEXT: vslw 2, 2, 3
+; CHECK-NEXT: xxlor 34, 34, 37
; CHECK-NEXT: blr
%f = call <4 x i32> @llvm.fshr.v4i32(<4 x i32> %x, <4 x i32> %x, <4 x i32> %z)
ret <4 x i32> %f
diff --git a/llvm/test/CodeGen/PowerPC/funnel-shift.ll b/llvm/test/CodeGen/PowerPC/funnel-shift.ll
index 9acc1ac5221..05d105bd6eb 100644
--- a/llvm/test/CodeGen/PowerPC/funnel-shift.ll
+++ b/llvm/test/CodeGen/PowerPC/funnel-shift.ll
@@ -18,9 +18,8 @@ declare <4 x i32> @llvm.fshr.v4i32(<4 x i32>, <4 x i32>, <4 x i32>)
define i32 @fshl_i32(i32 %x, i32 %y, i32 %z) {
; CHECK-LABEL: fshl_i32:
; CHECK: # %bb.0:
-; CHECK-NEXT: subfic 6, 5, 32
; CHECK-NEXT: andi. 5, 5, 31
-; CHECK-NEXT: clrlwi 6, 6, 27
+; CHECK-NEXT: subfic 6, 5, 32
; CHECK-NEXT: slw 5, 3, 5
; CHECK-NEXT: srw 4, 4, 6
; CHECK-NEXT: or 4, 5, 4
@@ -36,24 +35,19 @@ define i37 @fshl_i37(i37 %x, i37 %y, i37 %z) {
; CHECK-LABEL: fshl_i37:
; CHECK: # %bb.0:
; CHECK-NEXT: lis 6, -8857
-; CHECK-NEXT: subfic 7, 5, 37
; CHECK-NEXT: clrldi 5, 5, 27
; CHECK-NEXT: clrldi 4, 4, 27
; CHECK-NEXT: ori 6, 6, 51366
-; CHECK-NEXT: clrldi 7, 7, 27
; CHECK-NEXT: sldi 6, 6, 32
; CHECK-NEXT: oris 6, 6, 3542
; CHECK-NEXT: ori 6, 6, 31883
-; CHECK-NEXT: mulhdu 8, 7, 6
; CHECK-NEXT: mulhdu 6, 5, 6
-; CHECK-NEXT: rldicl 8, 8, 59, 5
; CHECK-NEXT: rldicl 6, 6, 59, 5
-; CHECK-NEXT: mulli 8, 8, 37
; CHECK-NEXT: mulli 6, 6, 37
-; CHECK-NEXT: sub 7, 7, 8
; CHECK-NEXT: subf. 5, 6, 5
-; CHECK-NEXT: srd 4, 4, 7
+; CHECK-NEXT: subfic 6, 5, 37
; CHECK-NEXT: sld 5, 3, 5
+; CHECK-NEXT: srd 4, 4, 6
; CHECK-NEXT: or 4, 5, 4
; CHECK-NEXT: isel 3, 3, 4, 2
; CHECK-NEXT: blr
@@ -130,9 +124,8 @@ define i8 @fshl_i8_const_fold() {
define i32 @fshr_i32(i32 %x, i32 %y, i32 %z) {
; CHECK-LABEL: fshr_i32:
; CHECK: # %bb.0:
-; CHECK-NEXT: subfic 6, 5, 32
; CHECK-NEXT: andi. 5, 5, 31
-; CHECK-NEXT: clrlwi 6, 6, 27
+; CHECK-NEXT: subfic 6, 5, 32
; CHECK-NEXT: srw 5, 4, 5
; CHECK-NEXT: slw 3, 3, 6
; CHECK-NEXT: or 3, 3, 5
@@ -148,24 +141,19 @@ define i37 @fshr_i37(i37 %x, i37 %y, i37 %z) {
; CHECK-LABEL: fshr_i37:
; CHECK: # %bb.0:
; CHECK-NEXT: lis 6, -8857
-; CHECK-NEXT: subfic 7, 5, 37
; CHECK-NEXT: clrldi 5, 5, 27
-; CHECK-NEXT: clrldi 9, 4, 27
; CHECK-NEXT: ori 6, 6, 51366
-; CHECK-NEXT: clrldi 7, 7, 27
; CHECK-NEXT: sldi 6, 6, 32
; CHECK-NEXT: oris 6, 6, 3542
; CHECK-NEXT: ori 6, 6, 31883
-; CHECK-NEXT: mulhdu 8, 5, 6
-; CHECK-NEXT: mulhdu 6, 7, 6
-; CHECK-NEXT: rldicl 8, 8, 59, 5
+; CHECK-NEXT: mulhdu 6, 5, 6
; CHECK-NEXT: rldicl 6, 6, 59, 5
-; CHECK-NEXT: mulli 8, 8, 37
; CHECK-NEXT: mulli 6, 6, 37
-; CHECK-NEXT: subf. 5, 8, 5
-; CHECK-NEXT: sub 6, 7, 6
-; CHECK-NEXT: srd 5, 9, 5
-; CHECK-NEXT: sld 3, 3, 6
+; CHECK-NEXT: subf. 5, 6, 5
+; CHECK-NEXT: clrldi 6, 4, 27
+; CHECK-NEXT: subfic 7, 5, 37
+; CHECK-NEXT: srd 5, 6, 5
+; CHECK-NEXT: sld 3, 3, 7
; CHECK-NEXT: or 3, 3, 5
; CHECK-NEXT: isel 3, 4, 3, 2
; CHECK-NEXT: blr
diff --git a/llvm/test/CodeGen/X86/funnel-shift-rot.ll b/llvm/test/CodeGen/X86/funnel-shift-rot.ll
index 79538785eaa..90574ef45ef 100644
--- a/llvm/test/CodeGen/X86/funnel-shift-rot.ll
+++ b/llvm/test/CodeGen/X86/funnel-shift-rot.ll
@@ -92,7 +92,7 @@ define i32 @rotl_i32(i32 %x, i32 %z) nounwind {
define <4 x i32> @rotl_v4i32(<4 x i32> %x, <4 x i32> %z) nounwind {
; X32-SSE2-LABEL: rotl_v4i32:
; X32-SSE2: # %bb.0:
-; X32-SSE2-NEXT: movdqa {{.*#+}} xmm3 = [32,32,32,32]
+; X32-SSE2-NEXT: pxor %xmm3, %xmm3
; X32-SSE2-NEXT: psubd %xmm1, %xmm3
; X32-SSE2-NEXT: movdqa {{.*#+}} xmm4 = [31,31,31,31]
; X32-SSE2-NEXT: pand %xmm4, %xmm3
@@ -132,7 +132,7 @@ define <4 x i32> @rotl_v4i32(<4 x i32> %x, <4 x i32> %z) nounwind {
; X64-AVX2-NEXT: vpbroadcastd {{.*#+}} xmm2 = [31,31,31,31]
; X64-AVX2-NEXT: vpand %xmm2, %xmm1, %xmm3
; X64-AVX2-NEXT: vpsllvd %xmm3, %xmm0, %xmm3
-; X64-AVX2-NEXT: vpbroadcastd {{.*#+}} xmm4 = [32,32,32,32]
+; X64-AVX2-NEXT: vpxor %xmm4, %xmm4, %xmm4
; X64-AVX2-NEXT: vpsubd %xmm1, %xmm4, %xmm1
; X64-AVX2-NEXT: vpand %xmm2, %xmm1, %xmm1
; X64-AVX2-NEXT: vpsrlvd %xmm1, %xmm0, %xmm0
@@ -226,27 +226,28 @@ define i64 @rotr_i64(i64 %x, i64 %z) nounwind {
; X32-SSE2-NEXT: pushl %esi
; X32-SSE2-NEXT: movl {{[0-9]+}}(%esp), %esi
; X32-SSE2-NEXT: movl {{[0-9]+}}(%esp), %edx
-; X32-SSE2-NEXT: movl {{[0-9]+}}(%esp), %eax
-; X32-SSE2-NEXT: movl %eax, %ecx
+; X32-SSE2-NEXT: movl {{[0-9]+}}(%esp), %ebx
+; X32-SSE2-NEXT: movl %ebx, %ecx
; X32-SSE2-NEXT: andl $63, %ecx
; X32-SSE2-NEXT: movl %edx, %edi
; X32-SSE2-NEXT: shrl %cl, %edi
-; X32-SSE2-NEXT: movl %esi, %ebx
-; X32-SSE2-NEXT: shrdl %cl, %edx, %ebx
-; X32-SSE2-NEXT: xorl %ebp, %ebp
+; X32-SSE2-NEXT: movl %esi, %ebp
+; X32-SSE2-NEXT: shrdl %cl, %edx, %ebp
+; X32-SSE2-NEXT: xorl %eax, %eax
; X32-SSE2-NEXT: testb $32, %cl
-; X32-SSE2-NEXT: cmovnel %edi, %ebx
-; X32-SSE2-NEXT: cmovnel %ebp, %edi
-; X32-SSE2-NEXT: movl $64, %ecx
-; X32-SSE2-NEXT: subl %eax, %ecx
-; X32-SSE2-NEXT: andl $63, %ecx
+; X32-SSE2-NEXT: cmovnel %edi, %ebp
+; X32-SSE2-NEXT: cmovnel %eax, %edi
+; X32-SSE2-NEXT: negl %ebx
+; X32-SSE2-NEXT: andl $63, %ebx
; X32-SSE2-NEXT: movl %esi, %eax
+; X32-SSE2-NEXT: movl %ebx, %ecx
; X32-SSE2-NEXT: shll %cl, %eax
; X32-SSE2-NEXT: shldl %cl, %esi, %edx
-; X32-SSE2-NEXT: testb $32, %cl
+; X32-SSE2-NEXT: testb $32, %bl
; X32-SSE2-NEXT: cmovnel %eax, %edx
-; X32-SSE2-NEXT: cmovnel %ebp, %eax
-; X32-SSE2-NEXT: orl %ebx, %eax
+; X32-SSE2-NEXT: movl $0, %ecx
+; X32-SSE2-NEXT: cmovnel %ecx, %eax
+; X32-SSE2-NEXT: orl %ebp, %eax
; X32-SSE2-NEXT: orl %edi, %edx
; X32-SSE2-NEXT: popl %esi
; X32-SSE2-NEXT: popl %edi
@@ -270,7 +271,7 @@ define <4 x i32> @rotr_v4i32(<4 x i32> %x, <4 x i32> %z) nounwind {
; X32-SSE2-LABEL: rotr_v4i32:
; X32-SSE2: # %bb.0:
; X32-SSE2-NEXT: movdqa {{.*#+}} xmm2 = [31,31,31,31]
-; X32-SSE2-NEXT: movdqa {{.*#+}} xmm3 = [32,32,32,32]
+; X32-SSE2-NEXT: pxor %xmm3, %xmm3
; X32-SSE2-NEXT: psubd %xmm1, %xmm3
; X32-SSE2-NEXT: movdqa %xmm1, %xmm4
; X32-SSE2-NEXT: pand %xmm2, %xmm4
@@ -310,7 +311,7 @@ define <4 x i32> @rotr_v4i32(<4 x i32> %x, <4 x i32> %z) nounwind {
; X64-AVX2-NEXT: vpbroadcastd {{.*#+}} xmm2 = [31,31,31,31]
; X64-AVX2-NEXT: vpand %xmm2, %xmm1, %xmm3
; X64-AVX2-NEXT: vpsrlvd %xmm3, %xmm0, %xmm3
-; X64-AVX2-NEXT: vpbroadcastd {{.*#+}} xmm4 = [32,32,32,32]
+; X64-AVX2-NEXT: vpxor %xmm4, %xmm4, %xmm4
; X64-AVX2-NEXT: vpsubd %xmm1, %xmm4, %xmm1
; X64-AVX2-NEXT: vpand %xmm2, %xmm1, %xmm1
; X64-AVX2-NEXT: vpsllvd %xmm1, %xmm0, %xmm0
@@ -396,7 +397,7 @@ declare i7 @llvm.fshr.i7(i7, i7, i7)
define i7 @fshl_i7() {
; ANY-LABEL: fshl_i7:
; ANY: # %bb.0:
-; ANY-NEXT: movb $112, %al
+; ANY-NEXT: movb $67, %al
; ANY-NEXT: ret{{[l|q]}}
%f = call i7 @llvm.fshl.i7(i7 112, i7 112, i7 9)
ret i7 %f
@@ -408,7 +409,7 @@ define i7 @fshl_i7() {
define i7 @fshr_i7() {
; ANY-LABEL: fshr_i7:
; ANY: # %bb.0:
-; ANY-NEXT: movb $125, %al
+; ANY-NEXT: movb $60, %al
; ANY-NEXT: ret{{[l|q]}}
%f = call i7 @llvm.fshr.i7(i7 113, i7 113, i7 16)
ret i7 %f
diff --git a/llvm/test/CodeGen/X86/funnel-shift.ll b/llvm/test/CodeGen/X86/funnel-shift.ll
index d4b3c0d91db..f349fca3eca 100644
--- a/llvm/test/CodeGen/X86/funnel-shift.ll
+++ b/llvm/test/CodeGen/X86/funnel-shift.ll
@@ -14,42 +14,29 @@ declare i32 @llvm.fshr.i32(i32, i32, i32)
declare i64 @llvm.fshr.i64(i64, i64, i64)
declare <4 x i32> @llvm.fshr.v4i32(<4 x i32>, <4 x i32>, <4 x i32>)
-; General case - all operands can be variables - x86 has shld, but that's not matched.
+; General case - all operands can be variables - x86 has shld, but the mask and cmov are not needed?
define i32 @fshl_i32(i32 %x, i32 %y, i32 %z) nounwind {
; X32-SSE2-LABEL: fshl_i32:
; X32-SSE2: # %bb.0:
-; X32-SSE2-NEXT: pushl %edi
; X32-SSE2-NEXT: pushl %esi
-; X32-SSE2-NEXT: movl {{[0-9]+}}(%esp), %esi
-; X32-SSE2-NEXT: movl {{[0-9]+}}(%esp), %edi
; X32-SSE2-NEXT: movl {{[0-9]+}}(%esp), %edx
-; X32-SSE2-NEXT: movl $32, %ecx
-; X32-SSE2-NEXT: subl %edx, %ecx
-; X32-SSE2-NEXT: # kill: def $cl killed $cl killed $ecx
-; X32-SSE2-NEXT: shrl %cl, %edi
-; X32-SSE2-NEXT: andl $31, %edx
+; X32-SSE2-NEXT: movl {{[0-9]+}}(%esp), %esi
+; X32-SSE2-NEXT: movl {{[0-9]+}}(%esp), %ecx
+; X32-SSE2-NEXT: andl $31, %ecx
; X32-SSE2-NEXT: movl %esi, %eax
-; X32-SSE2-NEXT: movl %edx, %ecx
-; X32-SSE2-NEXT: shll %cl, %eax
-; X32-SSE2-NEXT: orl %edi, %eax
-; X32-SSE2-NEXT: testl %edx, %edx
+; X32-SSE2-NEXT: shldl %cl, %edx, %eax
+; X32-SSE2-NEXT: testl %ecx, %ecx
; X32-SSE2-NEXT: cmovel %esi, %eax
; X32-SSE2-NEXT: popl %esi
-; X32-SSE2-NEXT: popl %edi
; X32-SSE2-NEXT: retl
;
; X64-AVX2-LABEL: fshl_i32:
; X64-AVX2: # %bb.0:
-; X64-AVX2-NEXT: movl $32, %ecx
-; X64-AVX2-NEXT: subl %edx, %ecx
-; X64-AVX2-NEXT: # kill: def $cl killed $cl killed $ecx
-; X64-AVX2-NEXT: shrl %cl, %esi
; X64-AVX2-NEXT: andl $31, %edx
; X64-AVX2-NEXT: movl %edi, %eax
; X64-AVX2-NEXT: movl %edx, %ecx
-; X64-AVX2-NEXT: shll %cl, %eax
-; X64-AVX2-NEXT: orl %esi, %eax
+; X64-AVX2-NEXT: shldl %cl, %esi, %eax
; X64-AVX2-NEXT: testl %edx, %edx
; X64-AVX2-NEXT: cmovel %edi, %eax
; X64-AVX2-NEXT: retq
@@ -66,58 +53,46 @@ define i37 @fshl_i37(i37 %x, i37 %y, i37 %z) nounwind {
; X32-SSE2-NEXT: pushl %ebx
; X32-SSE2-NEXT: pushl %edi
; X32-SSE2-NEXT: pushl %esi
-; X32-SSE2-NEXT: subl $8, %esp
+; X32-SSE2-NEXT: pushl %eax
; X32-SSE2-NEXT: movl {{[0-9]+}}(%esp), %edi
; X32-SSE2-NEXT: movl {{[0-9]+}}(%esp), %esi
; X32-SSE2-NEXT: andl $31, %esi
-; X32-SSE2-NEXT: movl {{[0-9]+}}(%esp), %ebx
; X32-SSE2-NEXT: movl {{[0-9]+}}(%esp), %eax
-; X32-SSE2-NEXT: movl %eax, %ebp
-; X32-SSE2-NEXT: andl $31, %ebp
-; X32-SSE2-NEXT: movl $37, %ecx
-; X32-SSE2-NEXT: subl %ebx, %ecx
-; X32-SSE2-NEXT: movl $0, %edx
-; X32-SSE2-NEXT: sbbl %eax, %edx
-; X32-SSE2-NEXT: andl $31, %edx
-; X32-SSE2-NEXT: pushl $0
-; X32-SSE2-NEXT: pushl $37
-; X32-SSE2-NEXT: pushl %edx
-; X32-SSE2-NEXT: pushl %ecx
-; X32-SSE2-NEXT: calll __umoddi3
-; X32-SSE2-NEXT: addl $16, %esp
-; X32-SSE2-NEXT: movl %eax, (%esp) # 4-byte Spill
-; X32-SSE2-NEXT: movl %eax, %ecx
-; X32-SSE2-NEXT: shrdl %cl, %esi, %edi
+; X32-SSE2-NEXT: andl $31, %eax
+; X32-SSE2-NEXT: movl {{[0-9]+}}(%esp), %ebp
; X32-SSE2-NEXT: pushl $0
; X32-SSE2-NEXT: pushl $37
-; X32-SSE2-NEXT: pushl %ebp
-; X32-SSE2-NEXT: pushl %ebx
+; X32-SSE2-NEXT: pushl %eax
+; X32-SSE2-NEXT: pushl {{[0-9]+}}(%esp)
; X32-SSE2-NEXT: calll __umoddi3
; X32-SSE2-NEXT: addl $16, %esp
-; X32-SSE2-NEXT: movl %edx, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Spill
-; X32-SSE2-NEXT: movl {{[0-9]+}}(%esp), %edx
-; X32-SSE2-NEXT: movl %edx, %ebp
-; X32-SSE2-NEXT: movl %eax, %ecx
+; X32-SSE2-NEXT: movl %eax, %ebx
+; X32-SSE2-NEXT: movl %edx, (%esp) # 4-byte Spill
+; X32-SSE2-NEXT: movl %ebp, %edx
+; X32-SSE2-NEXT: movl %ebx, %ecx
; X32-SSE2-NEXT: shll %cl, %ebp
-; X32-SSE2-NEXT: movl {{[0-9]+}}(%esp), %ebx
-; X32-SSE2-NEXT: shldl %cl, %edx, %ebx
-; X32-SSE2-NEXT: testb $32, %al
-; X32-SSE2-NEXT: cmovnel %ebp, %ebx
-; X32-SSE2-NEXT: movl $0, %edx
-; X32-SSE2-NEXT: cmovnel %edx, %ebp
-; X32-SSE2-NEXT: movl (%esp), %ecx # 4-byte Reload
+; X32-SSE2-NEXT: movl {{[0-9]+}}(%esp), %eax
+; X32-SSE2-NEXT: shldl %cl, %edx, %eax
+; X32-SSE2-NEXT: xorl %ecx, %ecx
+; X32-SSE2-NEXT: testb $32, %bl
+; X32-SSE2-NEXT: cmovnel %ebp, %eax
+; X32-SSE2-NEXT: cmovnel %ecx, %ebp
+; X32-SSE2-NEXT: xorl %edx, %edx
+; X32-SSE2-NEXT: movl $37, %ecx
+; X32-SSE2-NEXT: subl %ebx, %ecx
+; X32-SSE2-NEXT: shrdl %cl, %esi, %edi
; X32-SSE2-NEXT: shrl %cl, %esi
; X32-SSE2-NEXT: testb $32, %cl
; X32-SSE2-NEXT: cmovnel %esi, %edi
; X32-SSE2-NEXT: cmovnel %edx, %esi
-; X32-SSE2-NEXT: orl %ebx, %esi
+; X32-SSE2-NEXT: orl %eax, %esi
; X32-SSE2-NEXT: orl %ebp, %edi
-; X32-SSE2-NEXT: orl %eax, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Folded Spill
+; X32-SSE2-NEXT: orl %ebx, (%esp) # 4-byte Folded Spill
; X32-SSE2-NEXT: cmovel {{[0-9]+}}(%esp), %edi
; X32-SSE2-NEXT: cmovel {{[0-9]+}}(%esp), %esi
; X32-SSE2-NEXT: movl %edi, %eax
; X32-SSE2-NEXT: movl %esi, %edx
-; X32-SSE2-NEXT: addl $8, %esp
+; X32-SSE2-NEXT: addl $4, %esp
; X32-SSE2-NEXT: popl %esi
; X32-SSE2-NEXT: popl %edi
; X32-SSE2-NEXT: popl %ebx
@@ -126,37 +101,28 @@ define i37 @fshl_i37(i37 %x, i37 %y, i37 %z) nounwind {
;
; X64-AVX2-LABEL: fshl_i37:
; X64-AVX2: # %bb.0:
-; X64-AVX2-NEXT: pushq %rbx
-; X64-AVX2-NEXT: movq %rdx, %r10
-; X64-AVX2-NEXT: movabsq $137438953471, %r8 # imm = 0x1FFFFFFFFF
-; X64-AVX2-NEXT: andq %r8, %rsi
-; X64-AVX2-NEXT: movl $37, %r9d
-; X64-AVX2-NEXT: subq %rdx, %r9
-; X64-AVX2-NEXT: andq %r8, %r10
-; X64-AVX2-NEXT: movabsq $-2492803253203993461, %r11 # imm = 0xDD67C8A60DD67C8B
-; X64-AVX2-NEXT: movq %r10, %rax
-; X64-AVX2-NEXT: mulq %r11
-; X64-AVX2-NEXT: shrq $5, %rdx
-; X64-AVX2-NEXT: leaq (%rdx,%rdx,8), %rax
-; X64-AVX2-NEXT: leaq (%rdx,%rax,4), %rax
-; X64-AVX2-NEXT: subq %rax, %r10
-; X64-AVX2-NEXT: movq %rdi, %rbx
-; X64-AVX2-NEXT: movl %r10d, %ecx
-; X64-AVX2-NEXT: shlq %cl, %rbx
-; X64-AVX2-NEXT: andq %r9, %r8
+; X64-AVX2-NEXT: movq %rdx, %r8
+; X64-AVX2-NEXT: movabsq $137438953471, %rax # imm = 0x1FFFFFFFFF
+; X64-AVX2-NEXT: andq %rax, %rsi
+; X64-AVX2-NEXT: andq %rax, %r8
+; X64-AVX2-NEXT: movabsq $-2492803253203993461, %rcx # imm = 0xDD67C8A60DD67C8B
; X64-AVX2-NEXT: movq %r8, %rax
-; X64-AVX2-NEXT: mulq %r11
+; X64-AVX2-NEXT: mulq %rcx
; X64-AVX2-NEXT: shrq $5, %rdx
; X64-AVX2-NEXT: leaq (%rdx,%rdx,8), %rax
-; X64-AVX2-NEXT: leal (%rdx,%rax,4), %eax
-; X64-AVX2-NEXT: subl %eax, %r9d
-; X64-AVX2-NEXT: movl %r9d, %ecx
+; X64-AVX2-NEXT: leaq (%rdx,%rax,4), %rax
+; X64-AVX2-NEXT: subq %rax, %r8
+; X64-AVX2-NEXT: movq %rdi, %rax
+; X64-AVX2-NEXT: movl %r8d, %ecx
+; X64-AVX2-NEXT: shlq %cl, %rax
+; X64-AVX2-NEXT: movl $37, %ecx
+; X64-AVX2-NEXT: subl %r8d, %ecx
+; X64-AVX2-NEXT: # kill: def $cl killed $cl killed $ecx
; X64-AVX2-NEXT: shrq %cl, %rsi
-; X64-AVX2-NEXT: orq %rbx, %rsi
-; X64-AVX2-NEXT: testq %r10, %r10
+; X64-AVX2-NEXT: orq %rax, %rsi
+; X64-AVX2-NEXT: testq %r8, %r8
; X64-AVX2-NEXT: cmoveq %rdi, %rsi
; X64-AVX2-NEXT: movq %rsi, %rax
-; X64-AVX2-NEXT: popq %rbx
; X64-AVX2-NEXT: retq
%f = call i37 @llvm.fshl.i37(i37 %x, i37 %y, i37 %z)
ret i37 %f
@@ -246,47 +212,31 @@ define i8 @fshl_i8_const_fold() nounwind {
; Repeat everything for funnel shift right.
-; General case - all operands can be variables - x86 has 'shrd', but this doesn't match.
+; General case - all operands can be variables - x86 has 'shrd', but the mask and cmov are not needed?
define i32 @fshr_i32(i32 %x, i32 %y, i32 %z) nounwind {
; X32-SSE2-LABEL: fshr_i32:
; X32-SSE2: # %bb.0:
-; X32-SSE2-NEXT: pushl %ebx
-; X32-SSE2-NEXT: pushl %edi
; X32-SSE2-NEXT: pushl %esi
-; X32-SSE2-NEXT: movl {{[0-9]+}}(%esp), %esi
; X32-SSE2-NEXT: movl {{[0-9]+}}(%esp), %edx
-; X32-SSE2-NEXT: movl $32, %ebx
-; X32-SSE2-NEXT: subl %edx, %ebx
-; X32-SSE2-NEXT: andl $31, %edx
-; X32-SSE2-NEXT: movl %esi, %edi
-; X32-SSE2-NEXT: movl %edx, %ecx
-; X32-SSE2-NEXT: shrl %cl, %edi
-; X32-SSE2-NEXT: movl {{[0-9]+}}(%esp), %eax
-; X32-SSE2-NEXT: movl %ebx, %ecx
-; X32-SSE2-NEXT: shll %cl, %eax
-; X32-SSE2-NEXT: orl %edi, %eax
-; X32-SSE2-NEXT: testl %edx, %edx
+; X32-SSE2-NEXT: movl {{[0-9]+}}(%esp), %esi
+; X32-SSE2-NEXT: movl {{[0-9]+}}(%esp), %ecx
+; X32-SSE2-NEXT: andl $31, %ecx
+; X32-SSE2-NEXT: movl %esi, %eax
+; X32-SSE2-NEXT: shrdl %cl, %edx, %eax
+; X32-SSE2-NEXT: testl %ecx, %ecx
; X32-SSE2-NEXT: cmovel %esi, %eax
; X32-SSE2-NEXT: popl %esi
-; X32-SSE2-NEXT: popl %edi
-; X32-SSE2-NEXT: popl %ebx
; X32-SSE2-NEXT: retl
;
; X64-AVX2-LABEL: fshr_i32:
; X64-AVX2: # %bb.0:
-; X64-AVX2-NEXT: movl $32, %r8d
-; X64-AVX2-NEXT: subl %edx, %r8d
; X64-AVX2-NEXT: andl $31, %edx
; X64-AVX2-NEXT: movl %esi, %eax
; X64-AVX2-NEXT: movl %edx, %ecx
-; X64-AVX2-NEXT: shrl %cl, %eax
-; X64-AVX2-NEXT: movl %r8d, %ecx
-; X64-AVX2-NEXT: shll %cl, %edi
-; X64-AVX2-NEXT: orl %eax, %edi
+; X64-AVX2-NEXT: shrdl %cl, %edi, %eax
; X64-AVX2-NEXT: testl %edx, %edx
-; X64-AVX2-NEXT: cmovel %esi, %edi
-; X64-AVX2-NEXT: movl %edi, %eax
+; X64-AVX2-NEXT: cmovel %esi, %eax
; X64-AVX2-NEXT: retq
%f = call i32 @llvm.fshr.i32(i32 %x, i32 %y, i32 %z)
ret i32 %f
@@ -301,57 +251,42 @@ define i37 @fshr_i37(i37 %x, i37 %y, i37 %z) nounwind {
; X32-SSE2-NEXT: pushl %ebx
; X32-SSE2-NEXT: pushl %edi
; X32-SSE2-NEXT: pushl %esi
-; X32-SSE2-NEXT: pushl %eax
; X32-SSE2-NEXT: movl {{[0-9]+}}(%esp), %esi
; X32-SSE2-NEXT: andl $31, %esi
-; X32-SSE2-NEXT: movl {{[0-9]+}}(%esp), %ebp
; X32-SSE2-NEXT: movl {{[0-9]+}}(%esp), %eax
; X32-SSE2-NEXT: andl $31, %eax
+; X32-SSE2-NEXT: movl {{[0-9]+}}(%esp), %ebp
; X32-SSE2-NEXT: movl {{[0-9]+}}(%esp), %edi
; X32-SSE2-NEXT: pushl $0
; X32-SSE2-NEXT: pushl $37
; X32-SSE2-NEXT: pushl %eax
-; X32-SSE2-NEXT: pushl %ebp
+; X32-SSE2-NEXT: pushl {{[0-9]+}}(%esp)
; X32-SSE2-NEXT: calll __umoddi3
; X32-SSE2-NEXT: addl $16, %esp
; X32-SSE2-NEXT: movl %eax, %ebx
-; X32-SSE2-NEXT: movl %edx, (%esp) # 4-byte Spill
-; X32-SSE2-NEXT: movl $37, %eax
-; X32-SSE2-NEXT: subl %ebp, %eax
-; X32-SSE2-NEXT: movl $0, %edx
-; X32-SSE2-NEXT: sbbl {{[0-9]+}}(%esp), %edx
-; X32-SSE2-NEXT: andl $31, %edx
-; X32-SSE2-NEXT: movl {{[0-9]+}}(%esp), %ebp
-; X32-SSE2-NEXT: movl %ebx, %ecx
-; X32-SSE2-NEXT: shrdl %cl, %esi, %ebp
-; X32-SSE2-NEXT: pushl $0
-; X32-SSE2-NEXT: pushl $37
-; X32-SSE2-NEXT: pushl %edx
-; X32-SSE2-NEXT: pushl %eax
-; X32-SSE2-NEXT: calll __umoddi3
-; X32-SSE2-NEXT: addl $16, %esp
-; X32-SSE2-NEXT: movl %eax, %ecx
-; X32-SSE2-NEXT: movl {{[0-9]+}}(%esp), %edx
-; X32-SSE2-NEXT: movl %edx, %eax
-; X32-SSE2-NEXT: shll %cl, %eax
-; X32-SSE2-NEXT: shldl %cl, %edx, %edi
+; X32-SSE2-NEXT: movl $37, %ecx
+; X32-SSE2-NEXT: subl %eax, %ecx
+; X32-SSE2-NEXT: movl %ebp, %eax
+; X32-SSE2-NEXT: shll %cl, %ebp
+; X32-SSE2-NEXT: shldl %cl, %eax, %edi
+; X32-SSE2-NEXT: xorl %eax, %eax
; X32-SSE2-NEXT: testb $32, %cl
-; X32-SSE2-NEXT: cmovnel %eax, %edi
-; X32-SSE2-NEXT: movl $0, %edx
-; X32-SSE2-NEXT: cmovnel %edx, %eax
+; X32-SSE2-NEXT: cmovnel %ebp, %edi
+; X32-SSE2-NEXT: cmovnel %eax, %ebp
+; X32-SSE2-NEXT: movl {{[0-9]+}}(%esp), %eax
; X32-SSE2-NEXT: movl %ebx, %ecx
+; X32-SSE2-NEXT: shrdl %cl, %esi, %eax
; X32-SSE2-NEXT: shrl %cl, %esi
; X32-SSE2-NEXT: testb $32, %bl
-; X32-SSE2-NEXT: cmovnel %esi, %ebp
-; X32-SSE2-NEXT: cmovnel %edx, %esi
+; X32-SSE2-NEXT: cmovnel %esi, %eax
+; X32-SSE2-NEXT: movl $0, %ecx
+; X32-SSE2-NEXT: cmovnel %ecx, %esi
; X32-SSE2-NEXT: orl %edi, %esi
-; X32-SSE2-NEXT: orl %eax, %ebp
-; X32-SSE2-NEXT: orl %ebx, (%esp) # 4-byte Folded Spill
-; X32-SSE2-NEXT: cmovel {{[0-9]+}}(%esp), %ebp
+; X32-SSE2-NEXT: orl %ebp, %eax
+; X32-SSE2-NEXT: orl %ebx, %edx
+; X32-SSE2-NEXT: cmovel {{[0-9]+}}(%esp), %eax
; X32-SSE2-NEXT: cmovel {{[0-9]+}}(%esp), %esi
-; X32-SSE2-NEXT: movl %ebp, %eax
; X32-SSE2-NEXT: movl %esi, %edx
-; X32-SSE2-NEXT: addl $4, %esp
; X32-SSE2-NEXT: popl %esi
; X32-SSE2-NEXT: popl %edi
; X32-SSE2-NEXT: popl %ebx
@@ -360,37 +295,28 @@ define i37 @fshr_i37(i37 %x, i37 %y, i37 %z) nounwind {
;
; X64-AVX2-LABEL: fshr_i37:
; X64-AVX2: # %bb.0:
-; X64-AVX2-NEXT: pushq %rbx
-; X64-AVX2-NEXT: movq %rdx, %r10
-; X64-AVX2-NEXT: movabsq $137438953471, %r8 # imm = 0x1FFFFFFFFF
-; X64-AVX2-NEXT: movq %rsi, %r11
-; X64-AVX2-NEXT: andq %r8, %r11
-; X64-AVX2-NEXT: movl $37, %r9d
-; X64-AVX2-NEXT: subq %rdx, %r9
-; X64-AVX2-NEXT: andq %r8, %r10
-; X64-AVX2-NEXT: movabsq $-2492803253203993461, %rbx # imm = 0xDD67C8A60DD67C8B
-; X64-AVX2-NEXT: movq %r10, %rax
-; X64-AVX2-NEXT: mulq %rbx
-; X64-AVX2-NEXT: shrq $5, %rdx
-; X64-AVX2-NEXT: leaq (%rdx,%rdx,8), %rax
-; X64-AVX2-NEXT: leaq (%rdx,%rax,4), %rax
-; X64-AVX2-NEXT: subq %rax, %r10
-; X64-AVX2-NEXT: movl %r10d, %ecx
-; X64-AVX2-NEXT: shrq %cl, %r11
-; X64-AVX2-NEXT: andq %r9, %r8
+; X64-AVX2-NEXT: movq %rdx, %r8
+; X64-AVX2-NEXT: movabsq $137438953471, %rax # imm = 0x1FFFFFFFFF
+; X64-AVX2-NEXT: movq %rsi, %r9
+; X64-AVX2-NEXT: andq %rax, %r9
+; X64-AVX2-NEXT: andq %rax, %r8
+; X64-AVX2-NEXT: movabsq $-2492803253203993461, %rcx # imm = 0xDD67C8A60DD67C8B
; X64-AVX2-NEXT: movq %r8, %rax
-; X64-AVX2-NEXT: mulq %rbx
+; X64-AVX2-NEXT: mulq %rcx
; X64-AVX2-NEXT: shrq $5, %rdx
; X64-AVX2-NEXT: leaq (%rdx,%rdx,8), %rax
-; X64-AVX2-NEXT: leal (%rdx,%rax,4), %eax
-; X64-AVX2-NEXT: subl %eax, %r9d
-; X64-AVX2-NEXT: movl %r9d, %ecx
+; X64-AVX2-NEXT: leaq (%rdx,%rax,4), %rax
+; X64-AVX2-NEXT: subq %rax, %r8
+; X64-AVX2-NEXT: movl %r8d, %ecx
+; X64-AVX2-NEXT: shrq %cl, %r9
+; X64-AVX2-NEXT: movl $37, %ecx
+; X64-AVX2-NEXT: subl %r8d, %ecx
+; X64-AVX2-NEXT: # kill: def $cl killed $cl killed $ecx
; X64-AVX2-NEXT: shlq %cl, %rdi
-; X64-AVX2-NEXT: orq %r11, %rdi
-; X64-AVX2-NEXT: testq %r10, %r10
+; X64-AVX2-NEXT: orq %r9, %rdi
+; X64-AVX2-NEXT: testq %r8, %r8
; X64-AVX2-NEXT: cmoveq %rsi, %rdi
; X64-AVX2-NEXT: movq %rdi, %rax
-; X64-AVX2-NEXT: popq %rbx
; X64-AVX2-NEXT: retq
%f = call i37 @llvm.fshr.i37(i37 %x, i37 %y, i37 %z)
ret i37 %f
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