diff options
| -rw-r--r-- | llvm/lib/Target/PowerPC/PPCScheduleA2.td | 4 | ||||
| -rw-r--r-- | llvm/lib/Target/PowerPC/PPCScheduleE500mc.td | 12 | ||||
| -rw-r--r-- | llvm/lib/Target/PowerPC/PPCScheduleE5500.td | 16 | ||||
| -rw-r--r-- | llvm/lib/Target/PowerPC/PPCScheduleG5.td | 14 |
4 files changed, 23 insertions, 23 deletions
diff --git a/llvm/lib/Target/PowerPC/PPCScheduleA2.td b/llvm/lib/Target/PowerPC/PPCScheduleA2.td index 9cdfd0b996d..7cab1b2d462 100644 --- a/llvm/lib/Target/PowerPC/PPCScheduleA2.td +++ b/llvm/lib/Target/PowerPC/PPCScheduleA2.td @@ -1,10 +1,10 @@ //===- PPCScheduleA2.td - PPC A2 Scheduling Definitions --*- tablegen -*-===// -// +// // The LLVM Compiler Infrastructure // // This file is distributed under the University of Illinois Open Source // License. See LICENSE.TXT for details. -// +// //===----------------------------------------------------------------------===// // Primary reference: diff --git a/llvm/lib/Target/PowerPC/PPCScheduleE500mc.td b/llvm/lib/Target/PowerPC/PPCScheduleE500mc.td index 262c7150800..95e5ab64ed5 100644 --- a/llvm/lib/Target/PowerPC/PPCScheduleE500mc.td +++ b/llvm/lib/Target/PowerPC/PPCScheduleE500mc.td @@ -7,9 +7,9 @@ // //===----------------------------------------------------------------------===// // -// This file defines the itinerary class data for the Freescale e500mc 32-bit +// This file defines the itinerary class data for the Freescale e500mc 32-bit // Power processor. -// +// // All information is derived from the "e500mc Core Reference Manual", // Freescale Document Number E500MCRM, Rev. 1, 03/2012. // @@ -25,12 +25,12 @@ def E500_DIS1 : FuncUnit; // Dispatch stage - insn 2 // * Execute // 6 pipelined execution units: SFX0, SFX1, BU, FPU, LSU, CFX. // Some instructions can only execute in SFX0 but not SFX1. -// The CFX has a bypass path, allowing non-divide instructions to execute +// The CFX has a bypass path, allowing non-divide instructions to execute // while a divide instruction is executed. def E500_SFX0 : FuncUnit; // Simple unit 0 def E500_SFX1 : FuncUnit; // Simple unit 1 def E500_BU : FuncUnit; // Branch unit -def E500_CFX_DivBypass +def E500_CFX_DivBypass : FuncUnit; // CFX divide bypass path def E500_CFX_0 : FuncUnit; // CFX pipeline def E500_LSU_0 : FuncUnit; // LSU pipeline @@ -271,12 +271,12 @@ def PPCE500mcItineraries : ProcessorItineraries< [NoBypass, E500_GPR_Bypass]>, InstrItinData<IIC_FPGeneral, [InstrStage<1, [E500_DIS0, E500_DIS1], 0>, InstrStage<2, [E500_FPU_0]>], - [11, 1, 1], // Latency = 8, Repeat rate = 2 + [11, 1, 1], // Latency = 8, Repeat rate = 2 [E500_FPR_Bypass, E500_FPR_Bypass, E500_FPR_Bypass]>, InstrItinData<IIC_FPAddSub, [InstrStage<1, [E500_DIS0, E500_DIS1], 0>, InstrStage<4, [E500_FPU_0]>], - [13, 1, 1], // Latency = 10, Repeat rate = 4 + [13, 1, 1], // Latency = 10, Repeat rate = 4 [E500_FPR_Bypass, E500_FPR_Bypass, E500_FPR_Bypass]>, InstrItinData<IIC_FPCompare, [InstrStage<1, [E500_DIS0, E500_DIS1], 0>, diff --git a/llvm/lib/Target/PowerPC/PPCScheduleE5500.td b/llvm/lib/Target/PowerPC/PPCScheduleE5500.td index 642a5ae726e..d3673c0158e 100644 --- a/llvm/lib/Target/PowerPC/PPCScheduleE5500.td +++ b/llvm/lib/Target/PowerPC/PPCScheduleE5500.td @@ -7,9 +7,9 @@ // //===----------------------------------------------------------------------===// // -// This file defines the itinerary class data for the Freescale e5500 64-bit +// This file defines the itinerary class data for the Freescale e5500 64-bit // Power processor. -// +// // All information is derived from the "e5500 Core Reference Manual", // Freescale Document Number e5500RM, Rev. 1, 03/2012. // @@ -25,16 +25,16 @@ def E5500_DIS1 : FuncUnit; // * Execute // 6 pipelined execution units: SFX0, SFX1, BU, FPU, LSU, CFX. -// The CFX has a bypass path, allowing non-divide instructions to execute +// The CFX has a bypass path, allowing non-divide instructions to execute // while a divide instruction is being executed. def E5500_SFX0 : FuncUnit; // Simple unit 0 def E5500_SFX1 : FuncUnit; // Simple unit 1 def E5500_BU : FuncUnit; // Branch unit -def E5500_CFX_DivBypass +def E5500_CFX_DivBypass : FuncUnit; // CFX divide bypass path def E5500_CFX_0 : FuncUnit; // CFX pipeline stage 0 -def E5500_CFX_1 : FuncUnit; // CFX pipeline stage 1 +def E5500_CFX_1 : FuncUnit; // CFX pipeline stage 1 def E5500_LSU_0 : FuncUnit; // LSU pipeline def E5500_FPU_0 : FuncUnit; // FPU pipeline @@ -331,12 +331,12 @@ def PPCE5500Itineraries : ProcessorItineraries< [E5500_GPR_Bypass]>, InstrItinData<IIC_FPGeneral, [InstrStage<1, [E5500_DIS0, E5500_DIS1], 0>, InstrStage<1, [E5500_FPU_0]>], - [11, 2, 2], // Latency = 7, Repeat rate = 1 + [11, 2, 2], // Latency = 7, Repeat rate = 1 [E5500_FPR_Bypass, E5500_FPR_Bypass, E5500_FPR_Bypass]>, InstrItinData<IIC_FPAddSub, [InstrStage<1, [E5500_DIS0, E5500_DIS1], 0>, InstrStage<1, [E5500_FPU_0]>], - [11, 2, 2], // Latency = 7, Repeat rate = 1 + [11, 2, 2], // Latency = 7, Repeat rate = 1 [E5500_FPR_Bypass, E5500_FPR_Bypass, E5500_FPR_Bypass]>, InstrItinData<IIC_FPCompare, [InstrStage<1, [E5500_DIS0, E5500_DIS1], 0>, @@ -351,7 +351,7 @@ def PPCE5500Itineraries : ProcessorItineraries< E5500_FPR_Bypass, E5500_FPR_Bypass]>, InstrItinData<IIC_FPDivS, [InstrStage<1, [E5500_DIS0, E5500_DIS1], 0>, InstrStage<16, [E5500_FPU_0]>], - [24, 2, 2], // Latency = 20, Repeat rate = 16 + [24, 2, 2], // Latency = 20, Repeat rate = 16 [E5500_FPR_Bypass, E5500_FPR_Bypass, E5500_FPR_Bypass]>, InstrItinData<IIC_FPFused, [InstrStage<1, [E5500_DIS0, E5500_DIS1], 0>, diff --git a/llvm/lib/Target/PowerPC/PPCScheduleG5.td b/llvm/lib/Target/PowerPC/PPCScheduleG5.td index a001b592312..b2c2bd23c12 100644 --- a/llvm/lib/Target/PowerPC/PPCScheduleG5.td +++ b/llvm/lib/Target/PowerPC/PPCScheduleG5.td @@ -40,7 +40,7 @@ def G5Itineraries : ProcessorItineraries< InstrItinData<IIC_IntMulLI , [InstrStage<4, [G5_IU1, G5_IU2]>]>, InstrItinData<IIC_IntRFID , [InstrStage<1, [G5_IU2]>]>, InstrItinData<IIC_IntRotateD , [InstrStage<2, [G5_IU1, G5_IU2]>]>, - InstrItinData<IIC_IntRotateDI , [InstrStage<2, [G5_IU1, G5_IU2]>]>, + InstrItinData<IIC_IntRotateDI , [InstrStage<2, [G5_IU1, G5_IU2]>]>, InstrItinData<IIC_IntRotate , [InstrStage<4, [G5_IU1, G5_IU2]>]>, InstrItinData<IIC_IntShift , [InstrStage<2, [G5_IU1, G5_IU2]>]>, InstrItinData<IIC_IntTrapD , [InstrStage<1, [G5_IU1, G5_IU2]>]>, @@ -51,14 +51,14 @@ def G5Itineraries : ProcessorItineraries< InstrItinData<IIC_BrMCRX , [InstrStage<3, [G5_BPU]>]>, InstrItinData<IIC_LdStDCBF , [InstrStage<3, [G5_SLU]>]>, InstrItinData<IIC_LdStLoad , [InstrStage<3, [G5_SLU]>]>, - InstrItinData<IIC_LdStLoadUpd , [InstrStage<3, [G5_SLU]>]>, - InstrItinData<IIC_LdStLoadUpdX, [InstrStage<3, [G5_SLU]>]>, + InstrItinData<IIC_LdStLoadUpd , [InstrStage<3, [G5_SLU]>]>, + InstrItinData<IIC_LdStLoadUpdX, [InstrStage<3, [G5_SLU]>]>, InstrItinData<IIC_LdStStore , [InstrStage<3, [G5_SLU]>]>, - InstrItinData<IIC_LdStStoreUpd, [InstrStage<3, [G5_SLU]>]>, + InstrItinData<IIC_LdStStoreUpd, [InstrStage<3, [G5_SLU]>]>, InstrItinData<IIC_LdStDSS , [InstrStage<10, [G5_SLU]>]>, InstrItinData<IIC_LdStICBI , [InstrStage<40, [G5_SLU]>]>, InstrItinData<IIC_LdStSTFD , [InstrStage<4, [G5_SLU]>]>, - InstrItinData<IIC_LdStSTFDU , [InstrStage<4, [G5_SLU]>]>, + InstrItinData<IIC_LdStSTFDU , [InstrStage<4, [G5_SLU]>]>, InstrItinData<IIC_LdStLD , [InstrStage<3, [G5_SLU]>]>, InstrItinData<IIC_LdStLDU , [InstrStage<3, [G5_SLU]>]>, InstrItinData<IIC_LdStLDUX , [InstrStage<3, [G5_SLU]>]>, @@ -67,8 +67,8 @@ def G5Itineraries : ProcessorItineraries< InstrItinData<IIC_LdStLFDU , [InstrStage<5, [G5_SLU]>]>, InstrItinData<IIC_LdStLFDUX , [InstrStage<5, [G5_SLU]>]>, InstrItinData<IIC_LdStLHA , [InstrStage<5, [G5_SLU]>]>, - InstrItinData<IIC_LdStLHAU , [InstrStage<5, [G5_SLU]>]>, - InstrItinData<IIC_LdStLHAUX , [InstrStage<5, [G5_SLU]>]>, + InstrItinData<IIC_LdStLHAU , [InstrStage<5, [G5_SLU]>]>, + InstrItinData<IIC_LdStLHAUX , [InstrStage<5, [G5_SLU]>]>, InstrItinData<IIC_LdStLMW , [InstrStage<64, [G5_SLU]>]>, InstrItinData<IIC_LdStLVecX , [InstrStage<3, [G5_SLU]>]>, InstrItinData<IIC_LdStLWA , [InstrStage<5, [G5_SLU]>]>, |
