diff options
5 files changed, 67 insertions, 8 deletions
diff --git a/llvm/lib/Target/ARM/Disassembler/ARMDisassemblerCore.cpp b/llvm/lib/Target/ARM/Disassembler/ARMDisassemblerCore.cpp index ca67e5e2e6e..7900f9960ad 100644 --- a/llvm/lib/Target/ARM/Disassembler/ARMDisassemblerCore.cpp +++ b/llvm/lib/Target/ARM/Disassembler/ARMDisassemblerCore.cpp @@ -3286,13 +3286,19 @@ static bool DisassembleMiscFrm(MCInst &MI, unsigned Opcode, uint32_t insn, unsigned short NumOps, unsigned &NumOpsAdded, BO B) { if (MemBarrierInstr(insn)) { - // DMBsy, DSBsy, and ISBsy instructions have zero operand and are taken care - // of within the generic ARMBasicMCBuilder::BuildIt() method. - // // Inst{3-0} encodes the memory barrier option for the variants. - MI.addOperand(MCOperand::CreateImm(slice(insn, 3, 0))); - NumOpsAdded = 1; - return true; + unsigned opt = slice(insn, 3, 0); + switch (opt) { + case ARM_MB::SY: case ARM_MB::ST: + case ARM_MB::ISH: case ARM_MB::ISHST: + case ARM_MB::NSH: case ARM_MB::NSHST: + case ARM_MB::OSH: case ARM_MB::OSHST: + MI.addOperand(MCOperand::CreateImm(opt)); + NumOpsAdded = 1; + return true; + default: + return false; + } } switch (Opcode) { diff --git a/llvm/lib/Target/ARM/Disassembler/ThumbDisassemblerCore.h b/llvm/lib/Target/ARM/Disassembler/ThumbDisassemblerCore.h index 066a8e3178e..618526816f7 100644 --- a/llvm/lib/Target/ARM/Disassembler/ThumbDisassemblerCore.h +++ b/llvm/lib/Target/ARM/Disassembler/ThumbDisassemblerCore.h @@ -1616,8 +1616,7 @@ static inline bool t2MiscCtrlInstr(uint32_t insn) { // A8.6.26 // t2BXJ -> Rn // -// Miscellaneous control: t2DMBsy (and its t2DMB variants), -// t2DSBsy (and its t2DSB varianst), t2ISBsy, t2CLREX +// Miscellaneous control: // -> no operand (except pred-imm pred-ccr for CLREX, memory barrier variants) // // Hint: t2NOP, t2YIELD, t2WFE, t2WFI, t2SEV @@ -1634,6 +1633,22 @@ static bool DisassembleThumb2BrMiscCtrl(MCInst &MI, unsigned Opcode, if (NumOps == 0) return true; + if (Opcode == ARM::t2DMB || Opcode == ARM::t2DSB) { + // Inst{3-0} encodes the memory barrier option for the variants. + unsigned opt = slice(insn, 3, 0); + switch (opt) { + case ARM_MB::SY: case ARM_MB::ST: + case ARM_MB::ISH: case ARM_MB::ISHST: + case ARM_MB::NSH: case ARM_MB::NSHST: + case ARM_MB::OSH: case ARM_MB::OSHST: + MI.addOperand(MCOperand::CreateImm(opt)); + NumOpsAdded = 1; + return true; + default: + return false; + } + } + if (t2MiscCtrlInstr(insn)) return true; diff --git a/llvm/test/MC/Disassembler/ARM/invalid-DMB-thumb.txt b/llvm/test/MC/Disassembler/ARM/invalid-DMB-thumb.txt new file mode 100644 index 00000000000..0a4be6826cc --- /dev/null +++ b/llvm/test/MC/Disassembler/ARM/invalid-DMB-thumb.txt @@ -0,0 +1,16 @@ +# RUN: llvm-mc --disassemble %s -triple=thumb-apple-darwin9 |& grep {invalid instruction encoding} + +# Opcode=1908 Name=t2DMB Format=ARM_FORMAT_THUMBFRM(25) +# 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 +# ------------------------------------------------------------------------------------------------- +# | 1: 1: 1: 1| 0: 0: 1: 1| 1: 0: 1: 1| 1: 1: 1: 1| 1: 0: 0: 0| 1: 1: 1: 1| 0: 1: 0: 1| 0: 0: 0: 1| +# ------------------------------------------------------------------------------------------------- +# +# Inst{3-0} encodes the option: SY, ST, ISH, ISHST, NSH, NSHST, OSH, OSHST. +# Reject invalid encodings. +# +# See also A8.6.42 DSB +# All other encodings of option are reserved. It is IMPLEMENTATION DEFINED whether options +# other than SY are implemented. All unsupported and reserved options must execute as a full +# system DSB operation, but software must not rely on this behavior. +0xbf 0xf3 0x51 0x8f diff --git a/llvm/test/MC/Disassembler/ARM/invalid-DSB-arm.txt b/llvm/test/MC/Disassembler/ARM/invalid-DSB-arm.txt new file mode 100644 index 00000000000..afa2baff615 --- /dev/null +++ b/llvm/test/MC/Disassembler/ARM/invalid-DSB-arm.txt @@ -0,0 +1,16 @@ +# RUN: llvm-mc --disassemble %s -triple=arm-apple-darwin9 |& grep {invalid instruction encoding} + +# Opcode=102 Name=DSB Format=ARM_FORMAT_MISCFRM(26) +# 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 +# ------------------------------------------------------------------------------------------------- +# | 1: 1: 1: 1| 0: 1: 0: 1| 0: 1: 1: 1| 1: 1: 1: 1| 1: 1: 1: 1| 0: 0: 0: 0| 0: 1: 0: 0| 0: 0: 0: 0| +# ------------------------------------------------------------------------------------------------- +# +# Inst{3-0} encodes the option: SY, ST, ISH, ISHST, NSH, NSHST, OSH, OSHST. +# Reject invalid encodings. +# +# See also A8.6.42 DSB +# All other encodings of option are reserved. It is IMPLEMENTATION DEFINED whether options +# other than SY are implemented. All unsupported and reserved options must execute as a full +# system DSB operation, but software must not rely on this behavior. +0x40 0xf0 0x7f 0xf5 diff --git a/llvm/test/MC/Disassembler/ARM/thumb-tests.txt b/llvm/test/MC/Disassembler/ARM/thumb-tests.txt index 358ecf001b3..fe260a17b6b 100644 --- a/llvm/test/MC/Disassembler/ARM/thumb-tests.txt +++ b/llvm/test/MC/Disassembler/ARM/thumb-tests.txt @@ -202,3 +202,9 @@ # CHECK: vmov r1, r0, d11 0x50 0xec 0x1b 0x1b + +# CHECK: dsb nsh +0xbf 0xf3 0x47 0x8f + +# CHECK: isb +0xbf 0xf3 0x6f 0x8f |
