diff options
| -rw-r--r-- | llvm/lib/Target/ARM/ARMFastISel.cpp | 21 | ||||
| -rw-r--r-- | llvm/test/CodeGen/ARM/fast-isel-redefinition.ll | 11 |
2 files changed, 13 insertions, 19 deletions
diff --git a/llvm/lib/Target/ARM/ARMFastISel.cpp b/llvm/lib/Target/ARM/ARMFastISel.cpp index 0b63838129e..6f527e8795b 100644 --- a/llvm/lib/Target/ARM/ARMFastISel.cpp +++ b/llvm/lib/Target/ARM/ARMFastISel.cpp @@ -822,26 +822,9 @@ void ARMFastISel::ARMSimplifyAddress(Address &Addr, EVT VT) { // Since the offset is too large for the load/store instruction // get the reg+offset into a register. if (needsLowering) { - ARMCC::CondCodes Pred = ARMCC::AL; - unsigned PredReg = 0; - - TargetRegisterClass *RC = isThumb ? ARM::tGPRRegisterClass : - ARM::GPRRegisterClass; - unsigned BaseReg = createResultReg(RC); - - if (!isThumb) - emitARMRegPlusImmediate(*FuncInfo.MBB, FuncInfo.InsertPt, DL, - BaseReg, Addr.Base.Reg, Addr.Offset, - Pred, PredReg, - static_cast<const ARMBaseInstrInfo&>(TII)); - else { - assert(AFI->isThumb2Function()); - emitT2RegPlusImmediate(*FuncInfo.MBB, FuncInfo.InsertPt, DL, - BaseReg, Addr.Base.Reg, Addr.Offset, Pred, PredReg, - static_cast<const ARMBaseInstrInfo&>(TII)); - } + Addr.Base.Reg = FastEmit_ri_(MVT::i32, ISD::ADD, Addr.Base.Reg, + /*Op0IsKill*/false, Addr.Offset, MVT::i32); Addr.Offset = 0; - Addr.Base.Reg = BaseReg; } } diff --git a/llvm/test/CodeGen/ARM/fast-isel-redefinition.ll b/llvm/test/CodeGen/ARM/fast-isel-redefinition.ll new file mode 100644 index 00000000000..262432f807a --- /dev/null +++ b/llvm/test/CodeGen/ARM/fast-isel-redefinition.ll @@ -0,0 +1,11 @@ +; RUN: llc -O0 -regalloc=linearscan | grep "ldr r0" +; This isn't exactly a useful set of command-line options, but check that it +; doesn't crash. (It was crashing because a register was getting redefined.) + +target triple = "thumbv7-apple-macosx10.6.7" + +define i32 @f(i32* %x) nounwind ssp { + %y = getelementptr inbounds i32* %x, i32 5000 + %tmp103 = load i32* %y, align 4 + ret i32 %tmp103 +} |
