diff options
| -rw-r--r-- | llvm/lib/Target/ARM/Thumb2SizeReduction.cpp | 13 | ||||
| -rw-r--r-- | llvm/test/CodeGen/Thumb2/float-ops.ll | 2 |
2 files changed, 5 insertions, 10 deletions
diff --git a/llvm/lib/Target/ARM/Thumb2SizeReduction.cpp b/llvm/lib/Target/ARM/Thumb2SizeReduction.cpp index 40b07bec9ae..b5f195bd409 100644 --- a/llvm/lib/Target/ARM/Thumb2SizeReduction.cpp +++ b/llvm/lib/Target/ARM/Thumb2SizeReduction.cpp @@ -333,9 +333,7 @@ Thumb2SizeReduce::VerifyPredAndCC(MachineInstr *MI, const ReduceEntry &Entry, static bool VerifyLowRegs(MachineInstr *MI) { unsigned Opc = MI->getOpcode(); - bool isPCOk = (Opc == ARM::t2LDMIA_RET || Opc == ARM::t2LDMIA || - Opc == ARM::t2LDMDB || Opc == ARM::t2LDMIA_UPD || - Opc == ARM::t2LDMDB_UPD); + bool isPCOk = (Opc == ARM::t2LDMIA_RET || Opc == ARM::t2LDMIA_UPD); bool isLROk = (Opc == ARM::t2STMDB_UPD); bool isSPOk = isPCOk || isLROk; for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) { @@ -413,16 +411,14 @@ Thumb2SizeReduce::ReduceLoadStore(MachineBasicBlock &MBB, MachineInstr *MI, HasShift = true; OpNum = 4; break; - case ARM::t2LDMIA: - case ARM::t2LDMDB: { + case ARM::t2LDMIA: { unsigned BaseReg = MI->getOperand(0).getReg(); - if (!isARMLowRegister(BaseReg) || Entry.WideOpc != ARM::t2LDMIA) - return false; + assert(isARMLowRegister(BaseReg)); // For the non-writeback version (this one), the base register must be // one of the registers being loaded. bool isOK = false; - for (unsigned i = 4; i < MI->getNumOperands(); ++i) { + for (unsigned i = 3; i < MI->getNumOperands(); ++i) { if (MI->getOperand(i).getReg() == BaseReg) { isOK = true; break; @@ -446,7 +442,6 @@ Thumb2SizeReduce::ReduceLoadStore(MachineBasicBlock &MBB, MachineInstr *MI, break; } case ARM::t2LDMIA_UPD: - case ARM::t2LDMDB_UPD: case ARM::t2STMIA_UPD: case ARM::t2STMDB_UPD: { OpNum = 0; diff --git a/llvm/test/CodeGen/Thumb2/float-ops.ll b/llvm/test/CodeGen/Thumb2/float-ops.ll index e0396e60df4..7ec08f86665 100644 --- a/llvm/test/CodeGen/Thumb2/float-ops.ll +++ b/llvm/test/CodeGen/Thumb2/float-ops.ll @@ -109,7 +109,7 @@ entry: define double @load_d(double* %a) { entry: ; CHECK-LABEL: load_d: -; NONE: ldm.w r0, {r0, r1} +; NONE: ldm r0, {r0, r1} ; HARD: vldr d0, [r0] %0 = load double, double* %a, align 8 ret double %0 |
