diff options
| -rw-r--r-- | llvm/lib/Target/X86/MCTargetDesc/X86MCCodeEmitter.cpp | 6 | ||||
| -rw-r--r-- | llvm/test/MC/X86/x86-16.s | 8 |
2 files changed, 13 insertions, 1 deletions
diff --git a/llvm/lib/Target/X86/MCTargetDesc/X86MCCodeEmitter.cpp b/llvm/lib/Target/X86/MCTargetDesc/X86MCCodeEmitter.cpp index e44574c31e2..d3879e6c4cf 100644 --- a/llvm/lib/Target/X86/MCTargetDesc/X86MCCodeEmitter.cpp +++ b/llvm/lib/Target/X86/MCTargetDesc/X86MCCodeEmitter.cpp @@ -1161,7 +1161,11 @@ void X86MCCodeEmitter::EmitOpcodePrefix(uint64_t TSFlags, unsigned &CurByte, // Emit the address size opcode prefix as needed. bool need_address_override; - if (TSFlags & X86II::AdSize) { + // The AdSize prefix is only for 32-bit and 64-bit modes; in 16-bit mode we + // need the address override only for JECXZ instead. Since it's only one + // instruction, we special-case it rather than introducing an AdSize16 bit. + if ((!is16BitMode() && TSFlags & X86II::AdSize) || + (is16BitMode() && MI.getOpcode() == X86::JECXZ_32)) { need_address_override = true; } else if (MemOperand == -1) { need_address_override = false; diff --git a/llvm/test/MC/X86/x86-16.s b/llvm/test/MC/X86/x86-16.s index 9fdd8645e7a..e395a779f23 100644 --- a/llvm/test/MC/X86/x86-16.s +++ b/llvm/test/MC/X86/x86-16.s @@ -356,6 +356,14 @@ cmovnae %bx,%bx lcalll $0x2, $0x1234 +L1: + jcxz L1 +// CHECK: jcxz L1 +// CHECK: encoding: [0xe3,A] + jecxz L1 +// CHECK: jecxz L1 +// CHECK: encoding: [0x67,0xe3,A] + iret // CHECK: iretw // CHECK: encoding: [0xcf] |
