diff options
| -rw-r--r-- | llvm/lib/CodeGen/GlobalISel/IRTranslator.cpp | 5 | ||||
| -rw-r--r-- | llvm/test/CodeGen/AArch64/GlobalISel/arm64-irtranslator.ll | 8 |
2 files changed, 0 insertions, 13 deletions
diff --git a/llvm/lib/CodeGen/GlobalISel/IRTranslator.cpp b/llvm/lib/CodeGen/GlobalISel/IRTranslator.cpp index b5ecdbeacce..09bbbe2d8ae 100644 --- a/llvm/lib/CodeGen/GlobalISel/IRTranslator.cpp +++ b/llvm/lib/CodeGen/GlobalISel/IRTranslator.cpp @@ -1077,11 +1077,6 @@ bool IRTranslator::translateKnownIntrinsic(const CallInst &CI, Intrinsic::ID ID, .addDef(getOrCreateVReg(CI)) .addUse(getOrCreateVReg(*CI.getArgOperand(0))); return true; - case Intrinsic::floor: - MIRBuilder.buildInstr(TargetOpcode::G_FFLOOR) - .addDef(getOrCreateVReg(CI)) - .addUse(getOrCreateVReg(*CI.getArgOperand(0))); - return true; case Intrinsic::cos: MIRBuilder.buildInstr(TargetOpcode::G_FCOS) .addDef(getOrCreateVReg(CI)) diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/arm64-irtranslator.ll b/llvm/test/CodeGen/AArch64/GlobalISel/arm64-irtranslator.ll index 47519674e49..dd89f9a4c11 100644 --- a/llvm/test/CodeGen/AArch64/GlobalISel/arm64-irtranslator.ll +++ b/llvm/test/CodeGen/AArch64/GlobalISel/arm64-irtranslator.ll @@ -2324,14 +2324,6 @@ define float @test_sqrt_f32(float %x) { ret float %y } -declare float @llvm.floor.f32(float) -define float @test_floor_f32(float %x) { - ; CHECK-LABEL: name: test_floor_f32 - ; CHECK: %{{[0-9]+}}:_(s32) = G_FFLOOR %{{[0-9]+}} - %y = call float @llvm.floor.f32(float %x) - ret float %y -} - ; CHECK-LABEL: name: test_llvm.aarch64.neon.ld3.v4i32.p0i32 ; CHECK: %1:_(s384) = G_INTRINSIC_W_SIDE_EFFECTS intrinsic(@llvm.aarch64.neon.ld3), %0(p0) :: (load 48 from %ir.ptr, align 64) define void @test_llvm.aarch64.neon.ld3.v4i32.p0i32(i32* %ptr) { |
