diff options
| -rw-r--r-- | llvm/lib/Target/X86/X86ISelLowering.cpp | 9 |
1 files changed, 6 insertions, 3 deletions
diff --git a/llvm/lib/Target/X86/X86ISelLowering.cpp b/llvm/lib/Target/X86/X86ISelLowering.cpp index 18a998dba38..4dc8027d0bd 100644 --- a/llvm/lib/Target/X86/X86ISelLowering.cpp +++ b/llvm/lib/Target/X86/X86ISelLowering.cpp @@ -43479,16 +43479,19 @@ static SDValue combineAdd(SDNode *N, SelectionDAG &DAG, // FIXME: We have the (sub Y, (zext (vXi1 X))) -> (add (sext (vXi1 X)), Y) in // generic DAG combine without a legal type check, but adding this there // caused regressions. - if (Subtarget.hasAVX512() && VT.isVector()) { + if (VT.isVector()) { + const TargetLowering &TLI = DAG.getTargetLoweringInfo(); if (Op0.getOpcode() == ISD::ZERO_EXTEND && - Op0.getOperand(0).getValueType().getVectorElementType() == MVT::i1) { + Op0.getOperand(0).getValueType().getVectorElementType() == MVT::i1 && + TLI.isTypeLegal(Op0.getOperand(0).getValueType())) { SDLoc DL(N); SDValue SExt = DAG.getNode(ISD::SIGN_EXTEND, DL, VT, Op0.getOperand(0)); return DAG.getNode(ISD::SUB, DL, VT, Op1, SExt); } if (Op1.getOpcode() == ISD::ZERO_EXTEND && - Op1.getOperand(0).getValueType().getVectorElementType() == MVT::i1) { + Op1.getOperand(0).getValueType().getVectorElementType() == MVT::i1 && + TLI.isTypeLegal(Op1.getOperand(0).getValueType())) { SDLoc DL(N); SDValue SExt = DAG.getNode(ISD::SIGN_EXTEND, DL, VT, Op1.getOperand(0)); return DAG.getNode(ISD::SUB, DL, VT, Op0, SExt); |
