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-rw-r--r--llvm/lib/Target/PowerPC/PPCScheduleA2.td2
1 files changed, 1 insertions, 1 deletions
diff --git a/llvm/lib/Target/PowerPC/PPCScheduleA2.td b/llvm/lib/Target/PowerPC/PPCScheduleA2.td
index 1612cd2a0b8..324a0bfd982 100644
--- a/llvm/lib/Target/PowerPC/PPCScheduleA2.td
+++ b/llvm/lib/Target/PowerPC/PPCScheduleA2.td
@@ -143,7 +143,7 @@ def PPCA2Itineraries : ProcessorItineraries<
// A2 machine model for scheduling and other instruction cost heuristics.
def PPCA2Model : SchedMachineModel {
- let IssueWidth = 1; // 2 micro-ops are dispatched per cycle.
+ let IssueWidth = 1; // 1 instruction is dispatched per cycle.
let MinLatency = -1; // OperandCycles are interpreted as MinLatency.
let LoadLatency = 6; // Optimistic load latency assuming bypass.
// This is overriden by OperandCycles if the
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