diff options
| author | Hal Finkel <hfinkel@anl.gov> | 2013-11-27 03:12:56 +0000 |
|---|---|---|
| committer | Hal Finkel <hfinkel@anl.gov> | 2013-11-27 03:12:56 +0000 |
| commit | 8081ae913451f26153fa4eb459eb51a485c2910b (patch) | |
| tree | cf1143443ca48d80dede8060a99b0bc2f06c9e2f | |
| parent | d0ed730f924ecd1a39b9d979741dc627229d0cf9 (diff) | |
| download | bcm5719-llvm-8081ae913451f26153fa4eb459eb51a485c2910b.tar.gz bcm5719-llvm-8081ae913451f26153fa4eb459eb51a485c2910b.zip | |
Fix comment in PPCA2Model
llvm-svn: 195807
| -rw-r--r-- | llvm/lib/Target/PowerPC/PPCScheduleA2.td | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/llvm/lib/Target/PowerPC/PPCScheduleA2.td b/llvm/lib/Target/PowerPC/PPCScheduleA2.td index 1612cd2a0b8..324a0bfd982 100644 --- a/llvm/lib/Target/PowerPC/PPCScheduleA2.td +++ b/llvm/lib/Target/PowerPC/PPCScheduleA2.td @@ -143,7 +143,7 @@ def PPCA2Itineraries : ProcessorItineraries< // A2 machine model for scheduling and other instruction cost heuristics. def PPCA2Model : SchedMachineModel { - let IssueWidth = 1; // 2 micro-ops are dispatched per cycle. + let IssueWidth = 1; // 1 instruction is dispatched per cycle. let MinLatency = -1; // OperandCycles are interpreted as MinLatency. let LoadLatency = 6; // Optimistic load latency assuming bypass. // This is overriden by OperandCycles if the |
