diff options
| -rw-r--r-- | llvm/lib/Target/Hexagon/HexagonInstrInfo.td | 15 | ||||
| -rw-r--r-- | llvm/test/MC/Disassembler/Hexagon/alu32_perm.txt | 8 |
2 files changed, 22 insertions, 1 deletions
diff --git a/llvm/lib/Target/Hexagon/HexagonInstrInfo.td b/llvm/lib/Target/Hexagon/HexagonInstrInfo.td index 53124e80ea9..dba0e526182 100644 --- a/llvm/lib/Target/Hexagon/HexagonInstrInfo.td +++ b/llvm/lib/Target/Hexagon/HexagonInstrInfo.td @@ -91,7 +91,7 @@ multiclass CMP64_rr<string OpcStr, PatFrag OpNode> { } //===----------------------------------------------------------------------===// -// ALU32/ALU (Instructions with register-register form) +// ALU32/ALU + //===----------------------------------------------------------------------===// def SDTHexagonI64I32I32 : SDTypeProfile<1, 2, [SDTCisVT<0, i64>, SDTCisVT<1, i32>, SDTCisSameAs<1, 2>]>; @@ -155,6 +155,19 @@ class T_ALU32_3op_pred<string mnemonic, bits<3> MajOp, bits<3> MinOp, let Inst{4-0} = Rd; } +class T_ALU32_combineh<string Op1, string Op2, bits<3> MajOp, bits<3> MinOp, + bit OpsRev> + : T_ALU32_3op<"", MajOp, MinOp, OpsRev, 0> { + let AsmString = "$Rd = combine($Rs"#Op1#", $Rt"#Op2#")"; +} + +let isCodeGenOnly = 0 in { +def A2_combine_hh : T_ALU32_combineh<".h", ".h", 0b011, 0b100, 1>; +def A2_combine_hl : T_ALU32_combineh<".h", ".l", 0b011, 0b101, 1>; +def A2_combine_lh : T_ALU32_combineh<".l", ".h", 0b011, 0b110, 1>; +def A2_combine_ll : T_ALU32_combineh<".l", ".l", 0b011, 0b111, 1>; +} + multiclass T_ALU32_3op_p<string mnemonic, bits<3> MajOp, bits<3> MinOp, bit OpsRev> { def t : T_ALU32_3op_pred<mnemonic, MajOp, MinOp, OpsRev, 0, 0>; diff --git a/llvm/test/MC/Disassembler/Hexagon/alu32_perm.txt b/llvm/test/MC/Disassembler/Hexagon/alu32_perm.txt index ea1a0b61645..00ea8923b4e 100644 --- a/llvm/test/MC/Disassembler/Hexagon/alu32_perm.txt +++ b/llvm/test/MC/Disassembler/Hexagon/alu32_perm.txt @@ -1,5 +1,13 @@ # RUN: llvm-mc --triple hexagon -disassemble < %s | FileCheck %s +0x11 0xdf 0x95 0xf3 +# CHECK: r17 = combine(r31.h, r21.h) +0x11 0xdf 0xb5 0xf3 +# CHECK: r17 = combine(r31.h, r21.l) +0x11 0xdf 0xd5 0xf3 +# CHECK: r17 = combine(r31.l, r21.h) +0x11 0xdf 0xf5 0xf3 +# CHECK: r17 = combine(r31.l, r21.l) 0x11 0xc0 0x15 0x70 # CHECK: r17 = aslh(r21) 0x11 0xc0 0x35 0x70 |
