diff options
| -rw-r--r-- | llvm/lib/Target/Mips/MipsSEISelLowering.cpp | 14 | ||||
| -rw-r--r-- | llvm/test/CodeGen/Mips/dsp-vec-load-store.ll | 11 |
2 files changed, 25 insertions, 0 deletions
diff --git a/llvm/lib/Target/Mips/MipsSEISelLowering.cpp b/llvm/lib/Target/Mips/MipsSEISelLowering.cpp index 8b5a8746eb2..58c8e7ca9ed 100644 --- a/llvm/lib/Target/Mips/MipsSEISelLowering.cpp +++ b/llvm/lib/Target/Mips/MipsSEISelLowering.cpp @@ -53,6 +53,20 @@ MipsSETargetLowering::MipsSETargetLowering(MipsTargetMachine &TM) setOperationAction(ISD::BITCAST, VecTys[i], Legal); } + // Expand all truncating stores and extending loads. + unsigned FirstVT = (unsigned)MVT::FIRST_VECTOR_VALUETYPE; + unsigned LastVT = (unsigned)MVT::LAST_VECTOR_VALUETYPE; + + for (unsigned VT0 = FirstVT; VT0 <= LastVT; ++VT0) { + for (unsigned VT1 = FirstVT; VT1 <= LastVT; ++VT1) + setTruncStoreAction((MVT::SimpleValueType)VT0, + (MVT::SimpleValueType)VT1, Expand); + + setLoadExtAction(ISD::SEXTLOAD, (MVT::SimpleValueType)VT0, Expand); + setLoadExtAction(ISD::ZEXTLOAD, (MVT::SimpleValueType)VT0, Expand); + setLoadExtAction(ISD::EXTLOAD, (MVT::SimpleValueType)VT0, Expand); + } + setTargetDAGCombine(ISD::SHL); setTargetDAGCombine(ISD::SRA); setTargetDAGCombine(ISD::SRL); diff --git a/llvm/test/CodeGen/Mips/dsp-vec-load-store.ll b/llvm/test/CodeGen/Mips/dsp-vec-load-store.ll new file mode 100644 index 00000000000..7e4a8fedaa8 --- /dev/null +++ b/llvm/test/CodeGen/Mips/dsp-vec-load-store.ll @@ -0,0 +1,11 @@ +; RUN: llc -march=mipsel -mattr=+dsp < %s + +@g1 = common global <2 x i8> zeroinitializer, align 2 +@g0 = common global <2 x i8> zeroinitializer, align 2 + +define void @extend_load_trunc_store_v2i8() { +entry: + %0 = load <2 x i8>* @g1, align 2 + store <2 x i8> %0, <2 x i8>* @g0, align 2 + ret void +} |
