diff options
| -rw-r--r-- | llvm/include/llvm/IR/IntrinsicsARM.td | 2 | ||||
| -rw-r--r-- | llvm/test/CodeGen/ARM/fpscr-intrinsics.ll | 23 |
2 files changed, 24 insertions, 1 deletions
diff --git a/llvm/include/llvm/IR/IntrinsicsARM.td b/llvm/include/llvm/IR/IntrinsicsARM.td index 24239689a62..18ed24be56d 100644 --- a/llvm/include/llvm/IR/IntrinsicsARM.td +++ b/llvm/include/llvm/IR/IntrinsicsARM.td @@ -67,7 +67,7 @@ def int_arm_isb : GCCBuiltin<"__builtin_arm_isb">, MSBuiltin<"__isb">, // VFP def int_arm_get_fpscr : GCCBuiltin<"__builtin_arm_get_fpscr">, - Intrinsic<[llvm_i32_ty], [], [IntrNoMem]>; + Intrinsic<[llvm_i32_ty], [], []>; def int_arm_set_fpscr : GCCBuiltin<"__builtin_arm_set_fpscr">, Intrinsic<[], [llvm_i32_ty], []>; def int_arm_vcvtr : Intrinsic<[llvm_float_ty], [llvm_anyfloat_ty], diff --git a/llvm/test/CodeGen/ARM/fpscr-intrinsics.ll b/llvm/test/CodeGen/ARM/fpscr-intrinsics.ll new file mode 100644 index 00000000000..db24d0d6420 --- /dev/null +++ b/llvm/test/CodeGen/ARM/fpscr-intrinsics.ll @@ -0,0 +1,23 @@ +; RUN: llc < %s -O0 -mtriple=armv7-eabi -mcpu=cortex-a8 | FileCheck %s +; RUN: llc < %s -O3 -mtriple=armv7-eabi -mcpu=cortex-a8 | FileCheck %s + +; Function Attrs: nounwind +define void @fn1(i32* nocapture %p) local_unnamed_addr { +entry: + ; CHECK: vmrs r{{[0-9]+}}, fpscr + %0 = tail call i32 @llvm.arm.get.fpscr() + store i32 %0, i32* %p, align 4 + ; CHECK: vmsr fpscr, r{{[0-9]+}} + tail call void @llvm.arm.set.fpscr(i32 1) + ; CHECK: vmrs r{{[0-9]+}}, fpscr + %1 = tail call i32 @llvm.arm.get.fpscr() + %arrayidx1 = getelementptr inbounds i32, i32* %p, i32 1 + store i32 %1, i32* %arrayidx1, align 4 + ret void +} + +; Function Attrs: nounwind readonly +declare i32 @llvm.arm.get.fpscr() + +; Function Attrs: nounwind writeonly +declare void @llvm.arm.set.fpscr(i32) |
