diff options
| -rw-r--r-- | llvm/lib/Target/X86/X86ISelLowering.cpp | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/llvm/lib/Target/X86/X86ISelLowering.cpp b/llvm/lib/Target/X86/X86ISelLowering.cpp index 7bf1cc6875e..0a97bf39641 100644 --- a/llvm/lib/Target/X86/X86ISelLowering.cpp +++ b/llvm/lib/Target/X86/X86ISelLowering.cpp @@ -38312,8 +38312,8 @@ static SDValue combineToExtendVectorInReg(SDNode *N, SelectionDAG &DAG, if (InSVT != MVT::i32 && InSVT != MVT::i16 && InSVT != MVT::i8) return SDValue(); - // On AVX2+ targets, if the input/output types are both legal then we will be - // able to use SIGN_EXTEND/ZERO_EXTEND directly. + // If the input/output types are both legal then we have at least AVX1 and + // we will be able to use SIGN_EXTEND/ZERO_EXTEND directly. if (DAG.getTargetLoweringInfo().isTypeLegal(VT) && DAG.getTargetLoweringInfo().isTypeLegal(InVT)) return SDValue(); |
