diff options
| -rw-r--r-- | llvm/lib/CodeGen/GlobalISel/IRTranslator.cpp | 16 | ||||
| -rw-r--r-- | llvm/lib/CodeGen/MachineFunction.cpp | 1 | ||||
| -rw-r--r-- | llvm/test/CodeGen/AArch64/GlobalISel/debug-insts.ll | 15 |
3 files changed, 22 insertions, 10 deletions
diff --git a/llvm/lib/CodeGen/GlobalISel/IRTranslator.cpp b/llvm/lib/CodeGen/GlobalISel/IRTranslator.cpp index 4d1ac680a45..b6ce59dc120 100644 --- a/llvm/lib/CodeGen/GlobalISel/IRTranslator.cpp +++ b/llvm/lib/CodeGen/GlobalISel/IRTranslator.cpp @@ -598,18 +598,18 @@ bool IRTranslator::translateKnownIntrinsic(const CallInst &CI, Intrinsic::ID ID, return true; } - unsigned Reg = getOrCreateVReg(*Address); - auto RegDef = MRI->def_instr_begin(Reg); assert(DI.getVariable()->isValidLocationForIntrinsic( MIRBuilder.getDebugLoc()) && "Expected inlined-at fields to agree"); - - if (RegDef != MRI->def_instr_end() && - RegDef->getOpcode() == TargetOpcode::G_FRAME_INDEX) { - MIRBuilder.buildFIDbgValue(RegDef->getOperand(1).getIndex(), - DI.getVariable(), DI.getExpression()); + auto AI = dyn_cast<AllocaInst>(Address); + if (AI && AI->isStaticAlloca()) { + // Static allocas are tracked at the MF level, no need for DBG_VALUE + // instructions (in fact, they get ignored if they *do* exist). + MF->setVariableDbgInfo(DI.getVariable(), DI.getExpression(), + getOrCreateFrameIndex(*AI), DI.getDebugLoc()); } else - MIRBuilder.buildDirectDbgValue(Reg, DI.getVariable(), DI.getExpression()); + MIRBuilder.buildDirectDbgValue(getOrCreateVReg(*Address), + DI.getVariable(), DI.getExpression()); return true; } case Intrinsic::vaend: diff --git a/llvm/lib/CodeGen/MachineFunction.cpp b/llvm/lib/CodeGen/MachineFunction.cpp index 831e7d859bb..ef5e032f1af 100644 --- a/llvm/lib/CodeGen/MachineFunction.cpp +++ b/llvm/lib/CodeGen/MachineFunction.cpp @@ -169,6 +169,7 @@ void MachineFunction::clear() { InstructionRecycler.clear(Allocator); OperandRecycler.clear(Allocator); BasicBlockRecycler.clear(Allocator); + VariableDbgInfos.clear(); if (RegInfo) { RegInfo->~MachineRegisterInfo(); Allocator.Deallocate(RegInfo); diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/debug-insts.ll b/llvm/test/CodeGen/AArch64/GlobalISel/debug-insts.ll index 2c3def2e4a9..5a76661180f 100644 --- a/llvm/test/CodeGen/AArch64/GlobalISel/debug-insts.ll +++ b/llvm/test/CodeGen/AArch64/GlobalISel/debug-insts.ll @@ -1,8 +1,10 @@ ; RUN: llc -global-isel -mtriple=aarch64 %s -stop-after=irtranslator -o - | FileCheck %s - +; RUN: llc -mtriple=aarch64 -global-isel --global-isel-abort=0 -o /dev/null ; CHECK-LABEL: name: debug_declare -; CHECK: DBG_VALUE %stack.0.in.addr, 0, !11, !12, debug-location !13 +; CHECK: stack: +; CHECK: - { id: {{.*}}, name: in.addr, offset: {{.*}}, size: {{.*}}, alignment: {{.*}}, di-variable: '!11', +; CHECK-NEXT: di-expression: '!12', di-location: '!13' } ; CHECK: DBG_VALUE debug-use %0(s32), debug-use _, !11, !12, debug-location !13 define void @debug_declare(i32 %in) #0 !dbg !7 { entry: @@ -13,6 +15,15 @@ entry: ret void, !dbg !14 } +; CHECK-LABEL: name: debug_declare_vla +; CHECK: DBG_VALUE debug-use %{{[0-9]+}}(p0), debug-use _, !11, !12, debug-location !13 +define void @debug_declare_vla(i32 %in) #0 !dbg !7 { +entry: + %vla.addr = alloca i32, i32 %in + call void @llvm.dbg.declare(metadata i32* %vla.addr, metadata !11, metadata !12), !dbg !13 + ret void, !dbg !14 +} + ; CHECK-LABEL: name: debug_value ; CHECK: [[IN:%[0-9]+]](s32) = COPY %w0 define void @debug_value(i32 %in) #0 !dbg !7 { |
