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-rw-r--r--llvm/lib/Target/AMDGPU/AsmParser/AMDGPUAsmParser.cpp26
-rw-r--r--llvm/lib/Target/AMDGPU/SIInstrInfo.td4
-rw-r--r--llvm/test/MC/AMDGPU/vop3-gfx9.s83
-rw-r--r--llvm/test/MC/AMDGPU/vop_dpp.s70
-rw-r--r--llvm/test/MC/AMDGPU/vop_sdwa.s76
5 files changed, 223 insertions, 36 deletions
diff --git a/llvm/lib/Target/AMDGPU/AsmParser/AMDGPUAsmParser.cpp b/llvm/lib/Target/AMDGPU/AsmParser/AMDGPUAsmParser.cpp
index 1a58007c8ae..0dff52668c6 100644
--- a/llvm/lib/Target/AMDGPU/AsmParser/AMDGPUAsmParser.cpp
+++ b/llvm/lib/Target/AMDGPU/AsmParser/AMDGPUAsmParser.cpp
@@ -231,32 +231,32 @@ public:
return isRegKind() && !hasModifiers();
}
- bool isRegOrImmWithInputMods(MVT type) const {
- return isRegKind() || isInlinableImm(type);
+ bool isRegOrImmWithInputMods(unsigned RCID, MVT type) const {
+ return isRegClass(RCID) || isInlinableImm(type);
}
bool isRegOrImmWithInt16InputMods() const {
- return isRegOrImmWithInputMods(MVT::i16);
+ return isRegOrImmWithInputMods(AMDGPU::VS_32RegClassID, MVT::i16);
}
bool isRegOrImmWithInt32InputMods() const {
- return isRegOrImmWithInputMods(MVT::i32);
+ return isRegOrImmWithInputMods(AMDGPU::VS_32RegClassID, MVT::i32);
}
bool isRegOrImmWithInt64InputMods() const {
- return isRegOrImmWithInputMods(MVT::i64);
+ return isRegOrImmWithInputMods(AMDGPU::VS_64RegClassID, MVT::i64);
}
bool isRegOrImmWithFP16InputMods() const {
- return isRegOrImmWithInputMods(MVT::f16);
+ return isRegOrImmWithInputMods(AMDGPU::VS_32RegClassID, MVT::f16);
}
bool isRegOrImmWithFP32InputMods() const {
- return isRegOrImmWithInputMods(MVT::f32);
+ return isRegOrImmWithInputMods(AMDGPU::VS_32RegClassID, MVT::f32);
}
bool isRegOrImmWithFP64InputMods() const {
- return isRegOrImmWithInputMods(MVT::f64);
+ return isRegOrImmWithInputMods(AMDGPU::VS_64RegClassID, MVT::f64);
}
bool isVReg() const {
@@ -268,8 +268,12 @@ public:
isRegClass(AMDGPU::VReg_512RegClassID);
}
+ bool isVReg32() const {
+ return isRegClass(AMDGPU::VGPR_32RegClassID);
+ }
+
bool isVReg32OrOff() const {
- return isOff() || isRegClass(AMDGPU::VGPR_32RegClassID);
+ return isOff() || isVReg32();
}
bool isSDWAOperand(MVT type) const;
@@ -1350,9 +1354,9 @@ bool AMDGPUOperand::isRegClass(unsigned RCID) const {
bool AMDGPUOperand::isSDWAOperand(MVT type) const {
if (AsmParser->isVI())
- return isVReg();
+ return isVReg32();
else if (AsmParser->isGFX9())
- return isRegKind() || isInlinableImm(type);
+ return isRegClass(AMDGPU::VS_32RegClassID) || isInlinableImm(type);
else
return false;
}
diff --git a/llvm/lib/Target/AMDGPU/SIInstrInfo.td b/llvm/lib/Target/AMDGPU/SIInstrInfo.td
index 8438fc016be..5d5a80f09e6 100644
--- a/llvm/lib/Target/AMDGPU/SIInstrInfo.td
+++ b/llvm/lib/Target/AMDGPU/SIInstrInfo.td
@@ -863,7 +863,7 @@ def FP32SDWAInputMods : FPSDWAInputMods<FP32SDWAInputModsMatchClass>;
def FPVRegInputModsMatchClass : AsmOperandClass {
let Name = "VRegWithFPInputMods";
let ParserMethod = "parseRegWithFPInputMods";
- let PredicateMethod = "isVReg";
+ let PredicateMethod = "isVReg32";
}
def FPVRegInputMods : InputMods <FPVRegInputModsMatchClass> {
@@ -890,7 +890,7 @@ def Int32SDWAInputMods : IntSDWAInputMods<Int32SDWAInputModsMatchClass>;
def IntVRegInputModsMatchClass : AsmOperandClass {
let Name = "VRegWithIntInputMods";
let ParserMethod = "parseRegWithIntInputMods";
- let PredicateMethod = "isVReg";
+ let PredicateMethod = "isVReg32";
}
def IntVRegInputMods : InputMods <IntVRegInputModsMatchClass> {
diff --git a/llvm/test/MC/AMDGPU/vop3-gfx9.s b/llvm/test/MC/AMDGPU/vop3-gfx9.s
index b2324b9c44e..00d78496099 100644
--- a/llvm/test/MC/AMDGPU/vop3-gfx9.s
+++ b/llvm/test/MC/AMDGPU/vop3-gfx9.s
@@ -1,7 +1,8 @@
-// RUN: llvm-mc -arch=amdgcn -mcpu=gfx900 -show-encoding %s | FileCheck -check-prefix=GFX9 %s
+// RUN: not llvm-mc -arch=amdgcn -mcpu=gfx900 -show-encoding %s | FileCheck -check-prefix=GFX9 %s
// RUN: not llvm-mc -arch=amdgcn -mcpu=tahiti -show-encoding %s 2>&1 | FileCheck -check-prefix=NOVI %s
// RUN: not llvm-mc -arch=amdgcn -mcpu=hawaii -show-encoding %s 2>&1 | FileCheck -check-prefix=NOVI %s
// RUN: not llvm-mc -arch=amdgcn -mcpu=tonga -show-encoding %s 2>&1 | FileCheck -check-prefix=NOVI %s
+// RUN: not llvm-mc -arch=amdgcn -mcpu=gfx900 -show-encoding %s 2>&1 | FileCheck -check-prefix=NOGFX9 %s
v_lshl_add_u32 v1, v2, v3, v4
// GFX9: v_lshl_add_u32 v1, v2, v3, v4 ; encoding: [0x01,0x00,0xfd,0xd1,0x02,0x07,0x12,0x04]
@@ -453,3 +454,83 @@ v_screen_partition_4se_b32_e64 v5, v1
v_screen_partition_4se_b32_e64 v5, -1
// GXF9: [0x05,0x00,0x77,0xd1,0xc1,0x00,0x00,0x00]
// NOVI: error: instruction not supported on this GPU
+
+//===----------------------------------------------------------------------===//
+// Validate register size checks (bug 37943)
+//===----------------------------------------------------------------------===//
+
+// NOVI: error: invalid operand for instruction
+// NOGFX9: error: invalid operand for instruction
+v_add_f64 v[0:1], s0, v[0:1]
+
+// NOVI: error: invalid operand for instruction
+// NOGFX9: error: invalid operand for instruction
+v_add_f64 v[0:1], s[0:3], v[0:1]
+
+// NOVI: error: invalid operand for instruction
+// NOGFX9: error: invalid operand for instruction
+v_add_f64 v[0:1], v0, v[0:1]
+
+// NOVI: error: invalid operand for instruction
+// NOGFX9: error: invalid operand for instruction
+v_add_f64 v[0:1], v[0:2], v[0:1]
+
+// NOVI: error: invalid operand for instruction
+// NOGFX9: error: invalid operand for instruction
+v_add_f64 v[0:1], v[0:3], v[0:1]
+
+// NOVI: error: invalid operand for instruction
+// NOGFX9: error: invalid operand for instruction
+v_add_f64 v[0:1], v[0:1], v0
+
+// NOVI: error: invalid operand for instruction
+// NOGFX9: error: invalid operand for instruction
+v_add_f64 v[0:1], v[0:1], s0
+
+// NOVI: error: invalid operand for instruction
+// NOGFX9: error: invalid operand for instruction
+v_add_f32 v0, s[0:1], v0
+
+// NOVI: error: invalid operand for instruction
+// NOGFX9: error: invalid operand for instruction
+v_add_f32 v0, v[0:1], v0
+
+// NOVI: error: invalid operand for instruction
+// NOGFX9: error: invalid operand for instruction
+v_add_f32 v0, v0, s[0:1]
+
+// NOVI: error: invalid operand for instruction
+// NOGFX9: error: invalid operand for instruction
+v_add_f32 v0, v0, v[0:1]
+
+// NOVI: error: invalid operand for instruction
+// NOGFX9: error: invalid operand for instruction
+v_add_f16 v0, s[0:1], v0
+
+// NOVI: error: invalid operand for instruction
+// NOGFX9: error: invalid operand for instruction
+v_add_f16 v0, v[0:1], v0
+
+// NOVI: error: invalid operand for instruction
+// NOGFX9: error: invalid operand for instruction
+v_add_f16 v0, v0, s[0:1]
+
+// NOVI: error: invalid operand for instruction
+// NOGFX9: error: invalid operand for instruction
+v_add_f16 v0, v0, v[0:1]
+
+// NOVI: error: invalid operand for instruction
+// NOGFX9: error: invalid operand for instruction
+v_add_u16 v0, s[0:1], v0
+
+// NOVI: error: invalid operand for instruction
+// NOGFX9: error: invalid operand for instruction
+v_add_u16 v0, v[0:1], v0
+
+// NOVI: error: invalid operand for instruction
+// NOGFX9: error: invalid operand for instruction
+v_add_u16 v0, v0, s[0:1]
+
+// NOVI: error: invalid operand for instruction
+// NOGFX9: error: invalid operand for instruction
+v_add_u16 v0, v0, v[0:1]
diff --git a/llvm/test/MC/AMDGPU/vop_dpp.s b/llvm/test/MC/AMDGPU/vop_dpp.s
index eb68abb93f2..c059b80fd6d 100644
--- a/llvm/test/MC/AMDGPU/vop_dpp.s
+++ b/llvm/test/MC/AMDGPU/vop_dpp.s
@@ -599,32 +599,66 @@ v_cndmask_b32_dpp v5, v1, v2, vcc row_shl:15 row_mask:0x0 bank_mask:0x0
// Check that immideates and scalar regs are not supported
//===----------------------------------------------------------------------===//
-// NOSICI: error:
-// NOVI: error:
-// NOGFX9: error:
+// NOSICI: error: not a valid operand
+// NOVI: error: invalid operand for instruction
+// NOGFX9: error: invalid operand for instruction
v_mov_b32 v0, 1 row_shl:1 row_mask:0xa bank_mask:0x1 bound_ctrl:0
-// NOSICI: error:
-// NOVI: error:
-// NOGFX9: error:
+// NOSICI: error: not a valid operand
+// NOVI: error: invalid operand for instruction
+// NOGFX9: error: invalid operand for instruction
v_and_b32 v0, 42, v1 row_shl:1 row_mask:0xa bank_mask:0x1 bound_ctrl:0
-// NOSICI: error:
-// NOVI: error:
-// NOGFX9: error:
+// NOSICI: error: not a valid operand
+// NOVI: error: invalid operand for instruction
+// NOGFX9: error: invalid operand for instruction
v_add_f32 v0, v1, 345 row_shl:1 row_mask:0xa bank_mask:0x1 bound_ctrl:0
-// NOSICI: error:
-// NOVI: error:
-// NOGFX9: error:
+// NOSICI: error: not a valid operand
+// NOVI: error: invalid operand for instruction
+// NOGFX9: error: invalid operand for instruction
v_mov_b32 v0, s1 row_shl:1 row_mask:0xa bank_mask:0x1 bound_ctrl:0
-// NOSICI: error:
-// NOVI: error:
-// NOGFX9: error:
+// NOSICI: error: not a valid operand
+// NOVI: error: invalid operand for instruction
+// NOGFX9: error: invalid operand for instruction
v_and_b32 v0, s42, v1 row_shl:1 row_mask:0xa bank_mask:0x1 bound_ctrl:0
-// NOSICI: error:
-// NOVI: error:
-// NOGFX9: error:
+// NOSICI: error: not a valid operand
+// NOVI: error: invalid operand for instruction
+// NOGFX9: error: invalid operand for instruction
v_add_f32 v0, v1, s45 row_shl:1 row_mask:0xa bank_mask:0x1 bound_ctrl:0
+
+//===----------------------------------------------------------------------===//
+// Validate register size checks (bug 37943)
+//===----------------------------------------------------------------------===//
+
+// NOSICI: error: not a valid operand
+// NOVI: error: invalid operand for instruction
+// NOGFX9: error: invalid operand for instruction
+v_add_f32_dpp v5, v[1:2], v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
+
+// NOSICI: error: not a valid operand
+// NOVI: error: invalid operand for instruction
+// NOGFX9: error: invalid operand for instruction
+v_add_f32_dpp v5, v[1:3], v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
+
+// NOSICI: error: not a valid operand
+// NOVI: error: invalid operand for instruction
+// NOGFX9: error: invalid operand for instruction
+v_add_f32_dpp v5, v1, v[1:2] quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
+
+// NOSICI: error: not a valid operand
+// NOVI: error: invalid operand for instruction
+// NOGFX9: error: invalid operand for instruction
+v_add_f32_dpp v5, v1, v[1:4] quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
+
+// NOSICI: error: not a valid operand
+// NOVI: error: invalid operand for instruction
+// NOGFX9: error: invalid operand for instruction
+v_add_f16 v1, v[2:3], v3 row_shl:1 row_mask:0xa bank_mask:0x1 bound_ctrl:0
+
+// NOSICI: error: not a valid operand
+// NOVI: error: invalid operand for instruction
+// NOGFX9: error: invalid operand for instruction
+v_add_f16 v1, v3, v[2:3] row_shl:1 row_mask:0xa bank_mask:0x1 bound_ctrl:0
diff --git a/llvm/test/MC/AMDGPU/vop_sdwa.s b/llvm/test/MC/AMDGPU/vop_sdwa.s
index acd506494df..e191b05e9f0 100644
--- a/llvm/test/MC/AMDGPU/vop_sdwa.s
+++ b/llvm/test/MC/AMDGPU/vop_sdwa.s
@@ -708,8 +708,8 @@ v_mov_b32 v1, s2 dst_sel:BYTE_0 dst_unused:UNUSED_PRESERVE src0_sel:DWORD
// NOSICI: error:
// NOVI: error:
-// GFX9: v_mov_b32_sdwa v1, exec dst_sel:BYTE_0 dst_unused:UNUSED_PRESERVE src0_sel:DWORD ; encoding: [0xf9,0x02,0x02,0x7e,0x7e,0x10,0x86,0x00]
-v_mov_b32 v1, exec dst_sel:BYTE_0 dst_unused:UNUSED_PRESERVE src0_sel:DWORD
+// GFX9: v_mov_b32_sdwa v1, exec_lo dst_sel:BYTE_0 dst_unused:UNUSED_PRESERVE src0_sel:DWORD ; encoding: [0xf9,0x02,0x02,0x7e,0x7e,0x10,0x86,0x00]
+v_mov_b32 v1, exec_lo dst_sel:BYTE_0 dst_unused:UNUSED_PRESERVE src0_sel:DWORD
// NOSICI: error:
// NOVI: error:
@@ -729,7 +729,7 @@ v_add_f32 v0, v0, s22 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_s
// NOSICI: error:
// NOVI: error:
// NO: invalid operand (violates constant bus restrictions)
-v_add_f32 v0, exec, vcc dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:BYTE_2
+v_add_f32 v0, exec_lo, vcc dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:BYTE_2
// NOSICI: error:
// NOVI: error:
@@ -774,7 +774,7 @@ v_cmp_eq_f32_sdwa vcc, v1, ttmp15 src0_sel:WORD_1 src1_sel:BYTE_2
// NOSICI: error:
// NOVI: error:
// NOGFX9: error: invalid operand (violates constant bus restrictions)
-v_cmp_eq_f32_sdwa vcc, exec, vcc src0_sel:WORD_1 src1_sel:BYTE_2
+v_cmp_eq_f32_sdwa vcc, exec_lo, vcc_lo src0_sel:WORD_1 src1_sel:BYTE_2
// NOSICI: error:
// NOVI: error:
@@ -1081,3 +1081,71 @@ v_add_f32 v0, v0, v0 clamp div:2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WO
// NOVI: error:
// GFX9: v_screen_partition_4se_b32_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PRESERVE src0_sel:BYTE_0 ; encoding: [0xf9,0x6e,0x0a,0x7e,0x01,0x16,0x00,0x00]
v_screen_partition_4se_b32_sdwa v5, v1 src0_sel:BYTE_0
+
+//===----------------------------------------------------------------------===//
+// Validate register size checks (bug 37943)
+//===----------------------------------------------------------------------===//
+
+// NOSICI: error: invalid operand for instruction
+// NOGFX89: error: invalid operand for instruction
+v_add_f32 v0, s[0:1], v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:BYTE_2
+
+// NOSICI: error: invalid operand for instruction
+// NOGFX89: error: invalid operand for instruction
+v_add_f32 v0, s[0:3], v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:BYTE_2
+
+// NOSICI: error: invalid operand for instruction
+// NOGFX89: error: invalid operand for instruction
+v_add_f32 v0, v[0:1], v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:BYTE_2
+
+// NOSICI: error: invalid operand for instruction
+// NOGFX89: error: invalid operand for instruction
+v_add_f32 v0, v[0:2], v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:BYTE_2
+
+// NOSICI: error: invalid operand for instruction
+// NOGFX89: error: invalid operand for instruction
+v_add_f32 v0, v0, s[0:1] dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:BYTE_2
+
+// NOSICI: error: invalid operand for instruction
+// NOGFX89: error: invalid operand for instruction
+v_add_f32 v0, s0, v[0:1] dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:BYTE_2
+
+// NOSICI: error: invalid operand for instruction
+// NOGFX89: error: invalid operand for instruction
+v_add_f32 v0, s0, v[0:3] dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:BYTE_2
+
+// NOSICI: error: invalid operand for instruction
+// NOGFX89: error: invalid operand for instruction
+v_add_f16 v1, v[2:3], v3 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:BYTE_2
+
+// NOSICI: error: invalid operand for instruction
+// NOGFX89: error: invalid operand for instruction
+v_add_f16 v1, s[2:3], v3 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:BYTE_2
+
+// NOSICI: error: invalid operand for instruction
+// NOGFX89: error: invalid operand for instruction
+v_add_f16 v1, v2, v[2:3] dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:BYTE_2
+
+// NOSICI: error: invalid operand for instruction
+// NOGFX89: error: invalid operand for instruction
+v_add_f16 v1, v2, s[2:3] dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:BYTE_2
+
+// NOSICI: error: not a valid operand
+// NOVI: error: not a valid operand
+// NOGFX9: error: invalid operand for instruction
+v_add_u32 v1, v[2:3], v3 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:BYTE_2
+
+// NOSICI: error: not a valid operand
+// NOVI: error: not a valid operand
+// NOGFX9: error: invalid operand for instruction
+v_add_u32 v1, s[2:3], v3 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:BYTE_2
+
+// NOSICI: error: not a valid operand
+// NOVI: error: not a valid operand
+// NOGFX9: error: invalid operand for instruction
+v_add_u32 v1, v3, v[2:3] dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:BYTE_2
+
+// NOSICI: error: not a valid operand
+// NOVI: error: not a valid operand
+// NOGFX9: error: invalid operand for instruction
+v_add_u32 v1, v3, s[2:3] dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:BYTE_2
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