diff options
| -rw-r--r-- | llvm/lib/Target/X86/X86ISelLowering.cpp | 47 |
1 files changed, 24 insertions, 23 deletions
diff --git a/llvm/lib/Target/X86/X86ISelLowering.cpp b/llvm/lib/Target/X86/X86ISelLowering.cpp index 6bdd448f5b8..64585c8de0a 100644 --- a/llvm/lib/Target/X86/X86ISelLowering.cpp +++ b/llvm/lib/Target/X86/X86ISelLowering.cpp @@ -37667,34 +37667,35 @@ static SDValue PromoteMaskArithmetic(SDNode *N, SelectionDAG &DAG, /// unnecessary moves from SSE to integer registers. static SDValue convertIntLogicToFPLogic(SDNode *N, SelectionDAG &DAG, const X86Subtarget &Subtarget) { - unsigned FPOpcode = ISD::DELETED_NODE; - if (N->getOpcode() == ISD::AND) - FPOpcode = X86ISD::FAND; - else if (N->getOpcode() == ISD::OR) - FPOpcode = X86ISD::FOR; - else if (N->getOpcode() == ISD::XOR) - FPOpcode = X86ISD::FXOR; - - assert(FPOpcode != ISD::DELETED_NODE && - "Unexpected input node for FP logic conversion"); - EVT VT = N->getValueType(0); SDValue N0 = N->getOperand(0); SDValue N1 = N->getOperand(1); SDLoc DL(N); - if (N0.getOpcode() == ISD::BITCAST && N1.getOpcode() == ISD::BITCAST && - ((Subtarget.hasSSE1() && VT == MVT::i32) || - (Subtarget.hasSSE2() && VT == MVT::i64))) { - SDValue N00 = N0.getOperand(0); - SDValue N10 = N1.getOperand(0); - EVT N00Type = N00.getValueType(); - EVT N10Type = N10.getValueType(); - if (N00Type.isFloatingPoint() && N10Type.isFloatingPoint()) { - SDValue FPLogic = DAG.getNode(FPOpcode, DL, N00Type, N00, N10); - return DAG.getBitcast(VT, FPLogic); - } + + if (N0.getOpcode() != ISD::BITCAST || N1.getOpcode() != ISD::BITCAST) + return SDValue(); + + SDValue N00 = N0.getOperand(0); + SDValue N10 = N1.getOperand(0); + EVT N00Type = N00.getValueType(); + EVT N10Type = N10.getValueType(); + + // Ensure that both types are the same and are legal scalar fp types. + if (N00Type != N10Type || + !((Subtarget.hasSSE1() && N00Type == MVT::f32) || + (Subtarget.hasSSE2() && N00Type == MVT::f64))) + return SDValue(); + + unsigned FPOpcode; + switch (N->getOpcode()) { + default: llvm_unreachable("Unexpected input node for FP logic conversion"); + case ISD::AND: FPOpcode = X86ISD::FAND; break; + case ISD::OR: FPOpcode = X86ISD::FOR; break; + case ISD::XOR: FPOpcode = X86ISD::FXOR; break; } - return SDValue(); + + SDValue FPLogic = DAG.getNode(FPOpcode, DL, N00Type, N00, N10); + return DAG.getBitcast(VT, FPLogic); } /// If this is a zero/all-bits result that is bitwise-anded with a low bits |
