diff options
| -rw-r--r-- | llvm/lib/Target/Hexagon/Hexagon.td | 2 | ||||
| -rw-r--r-- | llvm/lib/Target/Hexagon/HexagonSubtarget.cpp | 4 | ||||
| -rw-r--r-- | llvm/lib/Target/Hexagon/HexagonSubtarget.h | 2 | ||||
| -rw-r--r-- | llvm/lib/Target/Hexagon/HexagonTargetMachine.cpp | 5 | ||||
| -rw-r--r-- | llvm/lib/Target/Hexagon/MCTargetDesc/HexagonMCTargetDesc.cpp | 12 | ||||
| -rw-r--r-- | llvm/lib/Target/Hexagon/MCTargetDesc/HexagonMCTargetDesc.h | 12 |
6 files changed, 22 insertions, 15 deletions
diff --git a/llvm/lib/Target/Hexagon/Hexagon.td b/llvm/lib/Target/Hexagon/Hexagon.td index 9e1c3357314..1189cfd488e 100644 --- a/llvm/lib/Target/Hexagon/Hexagon.td +++ b/llvm/lib/Target/Hexagon/Hexagon.td @@ -30,7 +30,7 @@ def ArchV60: SubtargetFeature<"v60", "HexagonArchVersion", "V60", "Hexagon V60"> // Hexagon ISA Extensions def ExtensionHVX: SubtargetFeature<"hvx", "UseHVXOps", "true", "Hexagon HVX instructions">; -def ExtensionHVXDbl: SubtargetFeature<"hvxDbl", "UseHVXDblOps", +def ExtensionHVXDbl: SubtargetFeature<"hvx-double", "UseHVXDblOps", "true", "Hexagon HVX Double instructions">; //===----------------------------------------------------------------------===// diff --git a/llvm/lib/Target/Hexagon/HexagonSubtarget.cpp b/llvm/lib/Target/Hexagon/HexagonSubtarget.cpp index cdd16df4cb1..aa0efd4f65e 100644 --- a/llvm/lib/Target/Hexagon/HexagonSubtarget.cpp +++ b/llvm/lib/Target/Hexagon/HexagonSubtarget.cpp @@ -61,9 +61,7 @@ void HexagonSubtarget::initializeEnvironment() { HexagonSubtarget & HexagonSubtarget::initializeSubtargetDependencies(StringRef CPU, StringRef FS) { - // Default architecture. - if (CPUString.empty()) - CPUString = "hexagonv60"; + CPUString = HEXAGON_MC::selectHexagonCPU(getTargetTriple(), CPU); static std::map<StringRef, HexagonArchEnum> CpuTable { { "hexagonv4", V4 }, diff --git a/llvm/lib/Target/Hexagon/HexagonSubtarget.h b/llvm/lib/Target/Hexagon/HexagonSubtarget.h index a259f556bdb..c7ae139c434 100644 --- a/llvm/lib/Target/Hexagon/HexagonSubtarget.h +++ b/llvm/lib/Target/Hexagon/HexagonSubtarget.h @@ -112,7 +112,7 @@ public: return Hexagon_SMALL_DATA_THRESHOLD; } const HexagonArchEnum &getHexagonArchVersion() const { - return HexagonArchVersion; + return HexagonArchVersion; } }; diff --git a/llvm/lib/Target/Hexagon/HexagonTargetMachine.cpp b/llvm/lib/Target/Hexagon/HexagonTargetMachine.cpp index ad5e8067db5..9dccd696c98 100644 --- a/llvm/lib/Target/Hexagon/HexagonTargetMachine.cpp +++ b/llvm/lib/Target/Hexagon/HexagonTargetMachine.cpp @@ -126,8 +126,9 @@ HexagonTargetMachine::HexagonTargetMachine(const Target &T, const Triple &TT, const TargetOptions &Options, Reloc::Model RM, CodeModel::Model CM, CodeGenOpt::Level OL) - : LLVMTargetMachine(T, "e-m:e-p:32:32-i1:32-i64:64-a:0-n32", TT, CPU, FS, - Options, RM, CM, OL), + : LLVMTargetMachine(T, "e-m:e-p:32:32:32-i64:64:64-i32:32:32-i16:16:16-" + "i1:8:8-f64:64:64-f32:32:32-v64:64:64-v32:32:32-a:0-" + "n16:32", TT, CPU, FS, Options, RM, CM, OL), TLOF(make_unique<HexagonTargetObjectFile>()) { initAsmInfo(); } diff --git a/llvm/lib/Target/Hexagon/MCTargetDesc/HexagonMCTargetDesc.cpp b/llvm/lib/Target/Hexagon/MCTargetDesc/HexagonMCTargetDesc.cpp index 9d950b84cc4..13409050746 100644 --- a/llvm/lib/Target/Hexagon/MCTargetDesc/HexagonMCTargetDesc.cpp +++ b/llvm/lib/Target/Hexagon/MCTargetDesc/HexagonMCTargetDesc.cpp @@ -48,6 +48,12 @@ cl::opt<bool> llvm::HexagonDisableDuplex ("mno-pairing", cl::desc("Disable looking for duplex instructions for Hexagon")); +StringRef HEXAGON_MC::selectHexagonCPU(const Triple &TT, StringRef CPU) { + if (CPU.empty()) + CPU = "hexagonv60"; + return CPU; +} + MCInstrInfo *llvm::createHexagonMCInstrInfo() { MCInstrInfo *X = new MCInstrInfo(); InitHexagonMCInstrInfo(X); @@ -62,10 +68,8 @@ static MCRegisterInfo *createHexagonMCRegisterInfo(const Triple &TT) { static MCSubtargetInfo * createHexagonMCSubtargetInfo(const Triple &TT, StringRef CPU, StringRef FS) { - StringRef CPUName = CPU; - if (CPU.empty()) - CPUName = "hexagonv5"; - return createHexagonMCSubtargetInfoImpl(TT, CPUName, FS); + CPU = HEXAGON_MC::selectHexagonCPU(TT, CPU); + return createHexagonMCSubtargetInfoImpl(TT, CPU, FS); } namespace { diff --git a/llvm/lib/Target/Hexagon/MCTargetDesc/HexagonMCTargetDesc.h b/llvm/lib/Target/Hexagon/MCTargetDesc/HexagonMCTargetDesc.h index 6fcfd487feb..a005a014416 100644 --- a/llvm/lib/Target/Hexagon/MCTargetDesc/HexagonMCTargetDesc.h +++ b/llvm/lib/Target/Hexagon/MCTargetDesc/HexagonMCTargetDesc.h @@ -41,17 +41,21 @@ extern const InstrStage HexagonStages[]; MCInstrInfo *createHexagonMCInstrInfo(); -MCCodeEmitter *createHexagonMCCodeEmitter(MCInstrInfo const &MCII, - MCRegisterInfo const &MRI, +MCCodeEmitter *createHexagonMCCodeEmitter(const MCInstrInfo &MCII, + const MCRegisterInfo &MRI, MCContext &MCT); -MCAsmBackend *createHexagonAsmBackend(Target const &T, - MCRegisterInfo const &MRI, +MCAsmBackend *createHexagonAsmBackend(const Target &T, + const MCRegisterInfo &MRI, const Triple &TT, StringRef CPU); MCObjectWriter *createHexagonELFObjectWriter(raw_pwrite_stream &OS, uint8_t OSABI, StringRef CPU); +namespace HEXAGON_MC { + StringRef selectHexagonCPU(const Triple &TT, StringRef CPU); +} + } // End llvm namespace // Define symbolic names for Hexagon registers. This defines a mapping from |
