diff options
| -rw-r--r-- | llvm/lib/Target/Mips/MipsInstrFPU.td | 68 | ||||
| -rw-r--r-- | llvm/test/MC/Mips/micromips/valid.s | 27 | ||||
| -rw-r--r-- | llvm/test/MC/Mips/mips1/invalid-mips2.s | 9 |
3 files changed, 72 insertions, 32 deletions
diff --git a/llvm/lib/Target/Mips/MipsInstrFPU.td b/llvm/lib/Target/Mips/MipsInstrFPU.td index 9ba7631f0a2..6d05731d8c4 100644 --- a/llvm/lib/Target/Mips/MipsInstrFPU.td +++ b/llvm/lib/Target/Mips/MipsInstrFPU.td @@ -397,21 +397,21 @@ let AdditionalPredicates = [NotInMicroMips] in { let DecoderNamespace = "MipsFP64" in { let AdditionalPredicates = [NotInMicroMips] in { def ROUND_L_S : ABSS_FT<"round.l.s", FGR64Opnd, FGR32Opnd, II_ROUND>, - ABSS_FM<0x8, 16>, FGR_64; + ABSS_FM<0x8, 16>, ISA_MIPS2, FGR_64; def ROUND_L_D64 : ABSS_FT<"round.l.d", FGR64Opnd, FGR64Opnd, II_ROUND>, - ABSS_FM<0x8, 17>, FGR_64; + ABSS_FM<0x8, 17>, INSN_MIPS3_32, FGR_64; def TRUNC_L_S : ABSS_FT<"trunc.l.s", FGR64Opnd, FGR32Opnd, II_TRUNC>, - ABSS_FM<0x9, 16>, FGR_64; + ABSS_FM<0x9, 16>, ISA_MIPS2, FGR_64; def TRUNC_L_D64 : ABSS_FT<"trunc.l.d", FGR64Opnd, FGR64Opnd, II_TRUNC>, - ABSS_FM<0x9, 17>, FGR_64; + ABSS_FM<0x9, 17>, INSN_MIPS3_32, FGR_64; def CEIL_L_S : ABSS_FT<"ceil.l.s", FGR64Opnd, FGR32Opnd, II_CEIL>, - ABSS_FM<0xa, 16>, FGR_64; + ABSS_FM<0xa, 16>, ISA_MIPS2, FGR_64; def CEIL_L_D64 : ABSS_FT<"ceil.l.d", FGR64Opnd, FGR64Opnd, II_CEIL>, - ABSS_FM<0xa, 17>, FGR_64; + ABSS_FM<0xa, 17>, INSN_MIPS3_32, FGR_64; def FLOOR_L_S : ABSS_FT<"floor.l.s", FGR64Opnd, FGR32Opnd, II_FLOOR>, - ABSS_FM<0xb, 16>, FGR_64; + ABSS_FM<0xb, 16>, ISA_MIPS2, FGR_64; def FLOOR_L_D64 : ABSS_FT<"floor.l.d", FGR64Opnd, FGR64Opnd, II_FLOOR>, - ABSS_FM<0xb, 17>, FGR_64; + ABSS_FM<0xb, 17>, INSN_MIPS3_32, FGR_64; } } @@ -457,14 +457,14 @@ let isPseudo = 1, isCodeGenOnly = 1 in { let AdditionalPredicates = [NotInMicroMips] in { def FABS_S : MMRel, ABSS_FT<"abs.s", FGR32Opnd, FGR32Opnd, II_ABS, fabs>, - ABSS_FM<0x5, 16>; - defm FABS : ABSS_M<"abs.d", II_ABS, fabs>, ABSS_FM<0x5, 17>; + ABSS_FM<0x5, 16>, ISA_MIPS1; + defm FABS : ABSS_M<"abs.d", II_ABS, fabs>, ABSS_FM<0x5, 17>, ISA_MIPS1; } def FNEG_S : MMRel, ABSS_FT<"neg.s", FGR32Opnd, FGR32Opnd, II_NEG, fneg>, - ABSS_FM<0x7, 16>; + ABSS_FM<0x7, 16>, ISA_MIPS1; let AdditionalPredicates = [NotInMicroMips] in { - defm FNEG : ABSS_M<"neg.d", II_NEG, fneg>, ABSS_FM<0x7, 17>; + defm FNEG : ABSS_M<"neg.d", II_NEG, fneg>, ABSS_FM<0x7, 17>, ISA_MIPS1; } let AdditionalPredicates = [NotInMicroMips] in { @@ -480,19 +480,21 @@ let AdditionalPredicates = [NotInMicroMips] in { /// Move Control Registers From/To CPU Registers let AdditionalPredicates = [NotInMicroMips] in { - def CFC1 : MMRel, MFC1_FT<"cfc1", GPR32Opnd, CCROpnd, II_CFC1>, MFC1_FM<2>; - def CTC1 : MMRel, MTC1_FT<"ctc1", CCROpnd, GPR32Opnd, II_CTC1>, MFC1_FM<6>; + def CFC1 : MMRel, MFC1_FT<"cfc1", GPR32Opnd, CCROpnd, II_CFC1>, MFC1_FM<2>, + ISA_MIPS1; + def CTC1 : MMRel, MTC1_FT<"ctc1", CCROpnd, GPR32Opnd, II_CTC1>, MFC1_FM<6>, + ISA_MIPS1; def MFC1 : MMRel, MFC1_FT<"mfc1", GPR32Opnd, FGR32Opnd, II_MFC1, - bitconvert>, MFC1_FM<0>; + bitconvert>, MFC1_FM<0>, ISA_MIPS1; def MFC1_D64 : MFC1_FT<"mfc1", GPR32Opnd, FGR64Opnd, II_MFC1>, MFC1_FM<0>, - FGR_64 { + ISA_MIPS1, FGR_64 { let DecoderNamespace = "MipsFP64"; } def MTC1 : MMRel, MTC1_FT<"mtc1", FGR32Opnd, GPR32Opnd, II_MTC1, - bitconvert>, MFC1_FM<4>; + bitconvert>, MFC1_FM<4>, ISA_MIPS1; def MTC1_D64 : MTC1_FT<"mtc1", FGR64Opnd, GPR32Opnd, II_MTC1>, MFC1_FM<4>, - FGR_64 { + ISA_MIPS1, FGR_64 { let DecoderNamespace = "MipsFP64"; } @@ -516,11 +518,11 @@ let AdditionalPredicates = [NotInMicroMips] in { bitconvert>, MFC1_FM<1>, ISA_MIPS3; let isMoveReg = 1 in { def FMOV_S : MMRel, ABSS_FT<"mov.s", FGR32Opnd, FGR32Opnd, II_MOV_S>, - ABSS_FM<0x6, 16>; + ABSS_FM<0x6, 16>, ISA_MIPS1; def FMOV_D32 : MMRel, ABSS_FT<"mov.d", AFGR64Opnd, AFGR64Opnd, II_MOV_D>, - ABSS_FM<0x6, 17>, FGR_32; + ABSS_FM<0x6, 17>, ISA_MIPS1, FGR_32; def FMOV_D64 : ABSS_FT<"mov.d", FGR64Opnd, FGR64Opnd, II_MOV_D>, - ABSS_FM<0x6, 17>, FGR_64 { + ABSS_FM<0x6, 17>, ISA_MIPS1, FGR_64 { let DecoderNamespace = "MipsFP64"; } } // isMoveReg @@ -529,9 +531,9 @@ let AdditionalPredicates = [NotInMicroMips] in { /// Floating Point Memory Instructions let AdditionalPredicates = [NotInMicroMips] in { def LWC1 : MMRel, LW_FT<"lwc1", FGR32Opnd, mem_simm16, II_LWC1, load>, - LW_FM<0x31>; + LW_FM<0x31>, ISA_MIPS1; def SWC1 : MMRel, SW_FT<"swc1", FGR32Opnd, mem_simm16, II_SWC1, store>, - LW_FM<0x39>; + LW_FM<0x39>, ISA_MIPS1; } let DecoderNamespace = "MipsFP64", AdditionalPredicates = [NotInMicroMips] in { @@ -596,17 +598,21 @@ let AdditionalPredicates = [IsNotNaCl, NotInMicroMips], /// Floating-point Aritmetic let AdditionalPredicates = [NotInMicroMips] in { def FADD_S : MMRel, ADDS_FT<"add.s", FGR32Opnd, II_ADD_S, 1, fadd>, - ADDS_FM<0x00, 16>; - defm FADD : ADDS_M<"add.d", II_ADD_D, 1, fadd>, ADDS_FM<0x00, 17>; + ADDS_FM<0x00, 16>, ISA_MIPS1; + defm FADD : ADDS_M<"add.d", II_ADD_D, 1, fadd>, ADDS_FM<0x00, 17>, + ISA_MIPS1; def FDIV_S : MMRel, ADDS_FT<"div.s", FGR32Opnd, II_DIV_S, 0, fdiv>, - ADDS_FM<0x03, 16>; - defm FDIV : ADDS_M<"div.d", II_DIV_D, 0, fdiv>, ADDS_FM<0x03, 17>; + ADDS_FM<0x03, 16>, ISA_MIPS1; + defm FDIV : ADDS_M<"div.d", II_DIV_D, 0, fdiv>, ADDS_FM<0x03, 17>, + ISA_MIPS1; def FMUL_S : MMRel, ADDS_FT<"mul.s", FGR32Opnd, II_MUL_S, 1, fmul>, - ADDS_FM<0x02, 16>; - defm FMUL : ADDS_M<"mul.d", II_MUL_D, 1, fmul>, ADDS_FM<0x02, 17>; + ADDS_FM<0x02, 16>, ISA_MIPS1; + defm FMUL : ADDS_M<"mul.d", II_MUL_D, 1, fmul>, ADDS_FM<0x02, 17>, + ISA_MIPS1; def FSUB_S : MMRel, ADDS_FT<"sub.s", FGR32Opnd, II_SUB_S, 0, fsub>, - ADDS_FM<0x01, 16>; - defm FSUB : ADDS_M<"sub.d", II_SUB_D, 0, fsub>, ADDS_FM<0x01, 17>; + ADDS_FM<0x01, 16>, ISA_MIPS1; + defm FSUB : ADDS_M<"sub.d", II_SUB_D, 0, fsub>, ADDS_FM<0x01, 17>, + ISA_MIPS1; } let AdditionalPredicates = [NotInMicroMips, HasMadd4] in { diff --git a/llvm/test/MC/Mips/micromips/valid.s b/llvm/test/MC/Mips/micromips/valid.s index da33c6151e0..9d94426f8a5 100644 --- a/llvm/test/MC/Mips/micromips/valid.s +++ b/llvm/test/MC/Mips/micromips/valid.s @@ -171,6 +171,8 @@ lwl $4, 16($5) # CHECK: lwl $4, 16($5) # encoding: [0x60,0x lwr $4, 16($5) # CHECK: lwr $4, 16($5) # encoding: [0x60,0x85,0x10,0x10] swl $4, 16($5) # CHECK: swl $4, 16($5) # encoding: [0x60,0x85,0x80,0x10] swr $4, 16($5) # CHECK: swr $4, 16($5) # encoding: [0x60,0x85,0x90,0x10] +mov.s $f0, $f2 # CHECK: mov.s $f0, $f2 # encoding: [0x54,0x02,0x00,0x7b] + # CHECK-NEXT: # <MCInst #{{[0-9]+}} FMOV_S_MM mov.d $f0, $f2 # CHECK: mov.d $f0, $f2 # encoding: [0x54,0x02,0x20,0x7b] # CHECK-NEXT: # <MCInst #{{[0-9]+}} FMOV_D32_MM movz $9, $6, $7 # CHECK: movz $9, $6, $7 # encoding: [0x00,0xe6,0x48,0x58] @@ -183,6 +185,10 @@ mfhi $6 # CHECK: mfhi $6 # encoding: [0x00,0x # FIXME: MTLO should also have its 16 bit implementation selected in micromips mtlo $6 # CHECK: mtlo $6 # encoding: [0x00,0x06,0x3d,0x7c] mflo $6 # CHECK: mflo $6 # encoding: [0x00,0x06,0x1d,0x7c] +mfc1 $3, $f4 # CHECK: mfc1 $3, $f4 # encoding: [0x54,0x64,0x20,0x3b] + # CHECK-NEXT: # <MCInst #{{.*}} MFC1_MM +mtc1 $2, $f4 # CHECK: mtc1 $2, $f4 # encoding: [0x54,0x44,0x28,0x3b] + # CHECK-NEXT: # <MCInst #{{.*}} MTC1_MM mfhc1 $4, $f0 # CHECK: mfhc1 $4, $f0 # encoding: [0x54,0x80,0x30,0x3b] # CHECK-NEXT: # <MCInst #{{[0-9]+}} MFHC1_D32_MM mthc1 $4, $f0 # CHECK: mthc1 $4, $f0 # encoding: [0x54,0x80,0x38,0x3b] @@ -282,13 +288,17 @@ syscall 396 # CHECK: syscall 396 # encoding: [0x01,0x # ldc1 $f7, 300($10) # -CHECK: ldc1 $f7, 300($10) # encoding: [0xbc,0xea,0x01,0x2c] ldc1 $f8, 300($10) # CHECK: ldc1 $f8, 300($10) # encoding: [0xbd,0x0a,0x01,0x2c] lwc1 $f2, 4($6) # CHECK: lwc1 $f2, 4($6) # encoding: [0x9c,0x46,0x00,0x04] + # CHECK-NEXT: # <MCInst #{{.*}} LWC1_MM sdc1 $f2, 4($6) # CHECK: sdc1 $f2, 4($6) # encoding: [0xb8,0x46,0x00,0x04] # FIXME: sdc1 should accept uneven registers # sdc1 $f7, 64($10) # -CHECK: sdc1 $f7, 64($10) # encoding: [0xb8,0xea,0x00,0x40] swc1 $f2, 4($6) # CHECK: swc1 $f2, 4($6) # encoding: [0x98,0x46,0x00,0x04] + # CHECK-NEXT: # <MCInst #{{.*}} SWC1_MM cfc1 $1, $2 # CHECK: cfc1 $1, $2 # encoding: [0x54,0x22,0x10,0x3b] + # CHECK: # <MCInst #{{.*}} CFC1_MM cfc2 $3, $4 # CHECK: cfc2 $3, $4 # encoding: [0x00,0x64,0xcd,0x3c] ctc1 $5, $6 # CHECK: ctc1 $5, $6 # encoding: [0x54,0xa6,0x18,0x3b] + # CHECK: # <MCInst #{{.*}} CTC1_MM ctc2 $7, $8 # CHECK: ctc2 $7, $8 # encoding: [0x00,0xe8,0xdd,0x3c] recip.s $f2, $f4 # CHECK: recip.s $f2, $f4 # encoding: [0x54,0x44,0x12,0x3b] recip.d $f2, $f4 # CHECK: recip.d $f2, $f4 # encoding: [0x54,0x44,0x52,0x3b] @@ -350,4 +360,19 @@ sync 1 # CHECK: sync 1 # encoding: [0x0 # CHECK-NEXT: # <MCInst #{{[0-9]+}} SYNC_MM synci 64($5) # CHECK: synci 64($5) # encoding: [0x42,0x05,0x00,0x40] # CHECK-NEXT: # <MCInst #{{[0-9]+}} SYNCI_MM - +add.s $f4, $f6, $f8 # CHECK: add.s $f4, $f6, $f8 # encoding: [0x55,0x06,0x20,0x30] + # CHECK-NEXT: # <MCInst {{.*}} FADD_S_MM +sub.s $f4, $f6, $f8 # CHECK: sub.s $f4, $f6, $f8 # encoding: [0x55,0x06,0x20,0x70] + # CHECK-NEXT: # <MCInst {{.*}} FSUB_S_MM +mul.s $f4, $f6, $f8 # CHECK: mul.s $f4, $f6, $f8 # encoding: [0x55,0x06,0x20,0xb0] + # CHECK-NEXT: # <MCInst {{.*}} FMUL_S_MM +div.s $f4, $f6, $f8 # CHECK: div.s $f4, $f6, $f8 # encoding: [0x55,0x06,0x20,0xf0] + # CHECK-NEXT: # <MCInst {{.*}} FDIV_S_MM +add.d $f4, $f6, $f8 # CHECK: add.d $f4, $f6, $f8 # encoding: [0x55,0x06,0x21,0x30] + # CHECK-NEXT: # <MCInst {{.*}} FADD_D32_MM +sub.d $f4, $f6, $f8 # CHECK: sub.d $f4, $f6, $f8 # encoding: [0x55,0x06,0x21,0x70] + # CHECK-NEXT: # <MCInst {{.*}} FSUB_D32_MM +mul.d $f4, $f6, $f8 # CHECK: mul.d $f4, $f6, $f8 # encoding: [0x55,0x06,0x21,0xb0] + # CHECK-NEXT: # <MCInst {{.*}} FMUL_D32_MM +div.d $f4, $f6, $f8 # CHECK: div.d $f4, $f6, $f8 # encoding: [0x55,0x06,0x21,0xf0] + # CHECK-NEXT: # <MCInst {{.*}} FDIV_D32_MM diff --git a/llvm/test/MC/Mips/mips1/invalid-mips2.s b/llvm/test/MC/Mips/mips1/invalid-mips2.s index 29bd223f291..2ca38472b02 100644 --- a/llvm/test/MC/Mips/mips1/invalid-mips2.s +++ b/llvm/test/MC/Mips/mips1/invalid-mips2.s @@ -46,3 +46,12 @@ trunc.w.d $f22,$f15 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled trunc.w.s $f28,$f30 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled sync # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled + round.l.s $f0, $f2 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled + round.l.d $f0, $f2 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled + trunc.l.s $f0, $f2 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled + trunc.l.d $f0, $f2 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled + ceil.l.s $f0, $f2 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled + ceil.l.d $f0, $f2 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled + floor.l.s $f0, $f2 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled + floor.l.d $f0, $f2 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled + |
