diff options
| -rw-r--r-- | llvm/lib/Target/AMDGPU/SIInstrInfo.cpp | 7 | ||||
| -rw-r--r-- | llvm/lib/Target/AMDGPU/SIInstrInfo.h | 3 | ||||
| -rw-r--r-- | llvm/test/CodeGen/AMDGPU/uniform-cfg.ll | 8 |
3 files changed, 12 insertions, 6 deletions
diff --git a/llvm/lib/Target/AMDGPU/SIInstrInfo.cpp b/llvm/lib/Target/AMDGPU/SIInstrInfo.cpp index 64416e80d59..7b232ba7b8b 100644 --- a/llvm/lib/Target/AMDGPU/SIInstrInfo.cpp +++ b/llvm/lib/Target/AMDGPU/SIInstrInfo.cpp @@ -1166,6 +1166,13 @@ unsigned SIInstrInfo::InsertBranch(MachineBasicBlock &MBB, return 2; } +bool SIInstrInfo::ReverseBranchCondition( + SmallVectorImpl<MachineOperand> &Cond) const { + assert(Cond.size() == 1); + Cond[0].setImm(-Cond[0].getImm()); + return false; +} + static void removeModOperands(MachineInstr &MI) { unsigned Opc = MI.getOpcode(); int Src0ModIdx = AMDGPU::getNamedOperandIdx(Opc, diff --git a/llvm/lib/Target/AMDGPU/SIInstrInfo.h b/llvm/lib/Target/AMDGPU/SIInstrInfo.h index 4e37372a991..46705cd0b7d 100644 --- a/llvm/lib/Target/AMDGPU/SIInstrInfo.h +++ b/llvm/lib/Target/AMDGPU/SIInstrInfo.h @@ -157,6 +157,9 @@ public: MachineBasicBlock *FBB, ArrayRef<MachineOperand> Cond, DebugLoc DL) const override; + bool ReverseBranchCondition( + SmallVectorImpl<MachineOperand> &Cond) const override; + bool areMemAccessesTriviallyDisjoint( MachineInstr *MIa, MachineInstr *MIb, AliasAnalysis *AA = nullptr) const override; diff --git a/llvm/test/CodeGen/AMDGPU/uniform-cfg.ll b/llvm/test/CodeGen/AMDGPU/uniform-cfg.ll index 87a4739ae22..dfc82f820cc 100644 --- a/llvm/test/CodeGen/AMDGPU/uniform-cfg.ll +++ b/llvm/test/CodeGen/AMDGPU/uniform-cfg.ll @@ -168,10 +168,8 @@ endif: ; SI-LABEL: {{^}}uniform_if_else_ret: ; SI: s_cmp_lg_i32 s{{[0-9]+}}, 0 -; SI-NEXT: s_cbranch_scc1 [[ELSE_LABEL:[0-9_A-Za-z]+]] -; SI-NEXT: s_branch [[IF_LABEL:[0-9_A-Za-z]+]] +; SI-NEXT: s_cbranch_scc0 [[IF_LABEL:[0-9_A-Za-z]+]] -; SI: [[ELSE_LABEL]]: ; SI: v_mov_b32_e32 [[TWO:v[0-9]+]], 2 ; SI: buffer_store_dword [[TWO]] ; SI: s_endpgm @@ -199,10 +197,8 @@ if.end: ; preds = %if.else, %if.then ; SI-LABEL: {{^}}uniform_if_else: ; SI: s_cmp_lg_i32 s{{[0-9]+}}, 0 -; SI-NEXT: s_cbranch_scc1 [[ELSE_LABEL:[0-9_A-Za-z]+]] -; SI-NEXT: s_branch [[IF_LABEL:[0-9_A-Za-z]+]] +; SI-NEXT: s_cbranch_scc0 [[IF_LABEL:[0-9_A-Za-z]+]] -; SI: [[ELSE_LABEL]]: ; SI: v_mov_b32_e32 [[TWO:v[0-9]+]], 2 ; SI: buffer_store_dword [[TWO]] ; SI: s_branch [[ENDIF_LABEL:[0-9_A-Za-z]+]] |
