diff options
| -rw-r--r-- | llvm/lib/Target/AArch64/AArch64InstrInfo.cpp | 3 | ||||
| -rw-r--r-- | llvm/test/CodeGen/AArch64/br-undef-cond.ll | 26 |
2 files changed, 28 insertions, 1 deletions
diff --git a/llvm/lib/Target/AArch64/AArch64InstrInfo.cpp b/llvm/lib/Target/AArch64/AArch64InstrInfo.cpp index c5bf3c79477..1451407de0e 100644 --- a/llvm/lib/Target/AArch64/AArch64InstrInfo.cpp +++ b/llvm/lib/Target/AArch64/AArch64InstrInfo.cpp @@ -261,8 +261,9 @@ void AArch64InstrInfo::instantiateCondBranch( BuildMI(&MBB, DL, get(AArch64::Bcc)).addImm(Cond[0].getImm()).addMBB(TBB); } else { // Folded compare-and-branch + // Note that we use addOperand instead of addReg to keep the flags. const MachineInstrBuilder MIB = - BuildMI(&MBB, DL, get(Cond[1].getImm())).addReg(Cond[2].getReg()); + BuildMI(&MBB, DL, get(Cond[1].getImm())).addOperand(Cond[2]); if (Cond.size() > 3) MIB.addImm(Cond[3].getImm()); MIB.addMBB(TBB); diff --git a/llvm/test/CodeGen/AArch64/br-undef-cond.ll b/llvm/test/CodeGen/AArch64/br-undef-cond.ll new file mode 100644 index 00000000000..12d0da2e4fc --- /dev/null +++ b/llvm/test/CodeGen/AArch64/br-undef-cond.ll @@ -0,0 +1,26 @@ +; RUN: llc < %s -verify-machineinstrs + +; Make sure we don't end up with a CBNZ of an undef v-/phys-reg. + +target datalayout = "e-m:o-i64:64-i128:128-n32:64-S128" +target triple = "arm64-apple-ios" + +declare void @bar(i8*) + +define void @foo(i8* %m, i32 %off0) { +.thread1653: + br i1 undef, label %0, label %.thread1880 + + %1 = icmp eq i32 undef, 0 + %.not = xor i1 %1, true + %brmerge = or i1 %.not, undef + br i1 %brmerge, label %.thread1880, label %.thread1705 + +.thread1705: + ret void + +.thread1880: + %m1652.ph = phi i8* [ %m, %0 ], [ null, %.thread1653 ] + call void @bar(i8* %m1652.ph) + ret void +} |
