diff options
| -rw-r--r-- | llvm/lib/Target/AArch64/AArch64InstructionSelector.cpp | 5 | ||||
| -rw-r--r-- | llvm/test/CodeGen/AArch64/GlobalISel/arm64-instructionselect.mir | 51 |
2 files changed, 56 insertions, 0 deletions
diff --git a/llvm/lib/Target/AArch64/AArch64InstructionSelector.cpp b/llvm/lib/Target/AArch64/AArch64InstructionSelector.cpp index 9c48d32897f..367fa00ee11 100644 --- a/llvm/lib/Target/AArch64/AArch64InstructionSelector.cpp +++ b/llvm/lib/Target/AArch64/AArch64InstructionSelector.cpp @@ -52,6 +52,8 @@ static unsigned selectBinaryOp(unsigned GenericOpc, unsigned RegBankID, switch (GenericOpc) { case TargetOpcode::G_OR: return AArch64::ORRWrr; + case TargetOpcode::G_XOR: + return AArch64::EORWrr; case TargetOpcode::G_AND: return AArch64::ANDWrr; case TargetOpcode::G_ADD: @@ -65,6 +67,8 @@ static unsigned selectBinaryOp(unsigned GenericOpc, unsigned RegBankID, switch (GenericOpc) { case TargetOpcode::G_OR: return AArch64::ORRXrr; + case TargetOpcode::G_XOR: + return AArch64::EORXrr; case TargetOpcode::G_AND: return AArch64::ANDXrr; case TargetOpcode::G_ADD: @@ -166,6 +170,7 @@ bool AArch64InstructionSelector::select(MachineInstr &I) const { } case TargetOpcode::G_OR: + case TargetOpcode::G_XOR: case TargetOpcode::G_AND: case TargetOpcode::G_ADD: case TargetOpcode::G_SUB: { diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/arm64-instructionselect.mir b/llvm/test/CodeGen/AArch64/GlobalISel/arm64-instructionselect.mir index 28a42460c3f..8efbaea4ac2 100644 --- a/llvm/test/CodeGen/AArch64/GlobalISel/arm64-instructionselect.mir +++ b/llvm/test/CodeGen/AArch64/GlobalISel/arm64-instructionselect.mir @@ -17,6 +17,9 @@ define void @or_s32_gpr() { ret void } define void @or_s64_gpr() { ret void } + define void @xor_s32_gpr() { ret void } + define void @xor_s64_gpr() { ret void } + define void @and_s32_gpr() { ret void } define void @and_s64_gpr() { ret void } @@ -176,6 +179,54 @@ body: | ... --- +# Same as add_s32_gpr, for G_XOR operations. +# CHECK-LABEL: name: xor_s32_gpr +name: xor_s32_gpr +isSSA: true + +# CHECK: registers: +# CHECK-NEXT: - { id: 0, class: gpr32 } +# CHECK-NEXT: - { id: 1, class: gpr32 } +registers: + - { id: 0, class: gpr } + - { id: 1, class: gpr } + +# CHECK: body: +# CHECK: %0 = COPY %w0 +# CHECK: %1 = EORWrr %0, %0 +body: | + bb.0: + liveins: %w0 + + %0(32) = COPY %w0 + %1(32) = G_XOR s32 %0, %0 +... + +--- +# Same as add_s64_gpr, for G_XOR operations. +# CHECK-LABEL: name: xor_s64_gpr +name: xor_s64_gpr +isSSA: true + +# CHECK: registers: +# CHECK-NEXT: - { id: 0, class: gpr64 } +# CHECK-NEXT: - { id: 1, class: gpr64 } +registers: + - { id: 0, class: gpr } + - { id: 1, class: gpr } + +# CHECK: body: +# CHECK: %0 = COPY %x0 +# CHECK: %1 = EORXrr %0, %0 +body: | + bb.0: + liveins: %x0 + + %0(64) = COPY %x0 + %1(64) = G_XOR s64 %0, %0 +... + +--- # Same as add_s32_gpr, for G_AND operations. # CHECK-LABEL: name: and_s32_gpr name: and_s32_gpr |
