17 files changed, 778 insertions, 0 deletions
diff --git a/llvm/lib/Target/AArch64/AArch64SVEInstrInfo.td b/llvm/lib/Target/AArch64/AArch64SVEInstrInfo.td
index 62dfdf1345a..7e2b152395a 100644
--- a/llvm/lib/Target/AArch64/AArch64SVEInstrInfo.td
+++ b/llvm/lib/Target/AArch64/AArch64SVEInstrInfo.td
@@ -1140,6 +1140,16 @@ let Predicates = [HasSVE2] in {
   defm SQABS_ZPmZ   : sve2_int_un_pred_arit<0b100, "sqabs">;
   defm SQNEG_ZPmZ   : sve2_int_un_pred_arit<0b101, "sqneg">;
 
+  // SVE2 saturating add/subtract
+  defm SQADD_ZPmZ  : sve2_int_arith_pred<0b110000, "sqadd">;
+  defm UQADD_ZPmZ  : sve2_int_arith_pred<0b110010, "uqadd">;
+  defm SQSUB_ZPmZ  : sve2_int_arith_pred<0b110100, "sqsub">;
+  defm UQSUB_ZPmZ  : sve2_int_arith_pred<0b110110, "uqsub">;
+  defm SUQADD_ZPmZ : sve2_int_arith_pred<0b111000, "suqadd">;
+  defm USQADD_ZPmZ : sve2_int_arith_pred<0b111010, "usqadd">;
+  defm SQSUBR_ZPmZ : sve2_int_arith_pred<0b111100, "sqsubr">;
+  defm UQSUBR_ZPmZ : sve2_int_arith_pred<0b111110, "uqsubr">;
+
   // SVE2 integer multiply long
   defm SQDMULLB_ZZZ : sve2_wide_int_arith_long<0b11000, "sqdmullb">;
   defm SQDMULLT_ZZZ : sve2_wide_int_arith_long<0b11001, "sqdmullt">;
diff --git a/llvm/test/MC/AArch64/SVE2/sqadd-diagnostics.s b/llvm/test/MC/AArch64/SVE2/sqadd-diagnostics.s
new file mode 100644
index 00000000000..4ba83c1e42e
--- /dev/null
+++ b/llvm/test/MC/AArch64/SVE2/sqadd-diagnostics.s
@@ -0,0 +1,37 @@
+// RUN: not llvm-mc -triple=aarch64 -show-encoding -mattr=+sve2 2>&1 < %s| FileCheck %s
+
+// --------------------------------------------------------------------------//
+// Source and Destination Registers must match
+
+sqadd z0.b, p0/m, z1.b, z2.b
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: operand must match destination register
+// CHECK-NEXT: sqadd z0.b, p0/m, z1.b, z2.b
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+
+// --------------------------------------------------------------------------//
+// Element sizes must match
+
+sqadd z0.b, p0/m, z0.d, z1.d
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
+// CHECK-NEXT: sqadd z0.b, p0/m, z0.d, z1.d
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+sqadd z0.b, p0/m, z0.b, z1.h
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
+// CHECK-NEXT: sqadd z0.b, p0/m, z0.b, z1.h
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+
+// --------------------------------------------------------------------------//
+// Invalid predicate
+
+sqadd z0.b, p0/z, z0.b, z1.b
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
+// CHECK-NEXT: sqadd z0.b, p0/z, z0.b, z1.b
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+sqadd z0.b, p8/m, z0.b, z1.b
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: restricted predicate has range [0, 7].
+// CHECK-NEXT: sqadd z0.b, p8/m, z0.b, z1.b
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
diff --git a/llvm/test/MC/AArch64/SVE2/sqadd.s b/llvm/test/MC/AArch64/SVE2/sqadd.s
new file mode 100644
index 00000000000..77c3ca9f499
--- /dev/null
+++ b/llvm/test/MC/AArch64/SVE2/sqadd.s
@@ -0,0 +1,59 @@
+// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sve2 < %s \
+// RUN:        | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
+// RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \
+// RUN:        | FileCheck %s --check-prefix=CHECK-ERROR
+// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve2 < %s \
+// RUN:        | llvm-objdump -d -mattr=+sve2 - | FileCheck %s --check-prefix=CHECK-INST
+// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve2 < %s \
+// RUN:        | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN
+
+sqadd z0.b, p0/m, z0.b, z1.b
+// CHECK-INST: sqadd z0.b, p0/m, z0.b, z1.b
+// CHECK-ENCODING: [0x20,0x80,0x18,0x44]
+// CHECK-ERROR: instruction requires: sve2
+// CHECK-UNKNOWN: 20 80 18 44 <unknown>
+
+sqadd z0.h, p0/m, z0.h, z1.h
+// CHECK-INST: sqadd z0.h, p0/m, z0.h, z1.h
+// CHECK-ENCODING: [0x20,0x80,0x58,0x44]
+// CHECK-ERROR: instruction requires: sve2
+// CHECK-UNKNOWN: 20 80 58 44 <unknown>
+
+sqadd z29.s, p7/m, z29.s, z30.s
+// CHECK-INST: sqadd z29.s, p7/m, z29.s, z30.s
+// CHECK-ENCODING: [0xdd,0x9f,0x98,0x44]
+// CHECK-ERROR: instruction requires: sve2
+// CHECK-UNKNOWN: dd 9f 98 44 <unknown>
+
+sqadd z31.d, p7/m, z31.d, z30.d
+// CHECK-INST: sqadd z31.d, p7/m, z31.d, z30.d
+// CHECK-ENCODING: [0xdf,0x9f,0xd8,0x44]
+// CHECK-ERROR: instruction requires: sve2
+// CHECK-UNKNOWN: df 9f d8 44 <unknown>
+
+// --------------------------------------------------------------------------//
+// Test compatibility with MOVPRFX instruction.
+
+movprfx z31.d, p0/z, z6.d
+// CHECK-INST: movprfx z31.d, p0/z, z6.d
+// CHECK-ENCODING: [0xdf,0x20,0xd0,0x04]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: df 20 d0 04 <unknown>
+
+sqadd z31.d, p0/m, z31.d, z30.d
+// CHECK-INST: sqadd z31.d, p0/m, z31.d, z30.d
+// CHECK-ENCODING: [0xdf,0x83,0xd8,0x44]
+// CHECK-ERROR: instruction requires: sve2
+// CHECK-UNKNOWN: df 83 d8 44 <unknown>
+
+movprfx z31, z6
+// CHECK-INST: movprfx z31, z6
+// CHECK-ENCODING: [0xdf,0xbc,0x20,0x04]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: df bc 20 04 <unknown>
+
+sqadd z31.d, p7/m, z31.d, z30.d
+// CHECK-INST: sqadd z31.d, p7/m, z31.d, z30.d
+// CHECK-ENCODING: [0xdf,0x9f,0xd8,0x44]
+// CHECK-ERROR: instruction requires: sve2
+// CHECK-UNKNOWN: df 9f d8 44 <unknown>
diff --git a/llvm/test/MC/AArch64/SVE2/sqsub-diagnostics.s b/llvm/test/MC/AArch64/SVE2/sqsub-diagnostics.s
new file mode 100644
index 00000000000..9960dde0201
--- /dev/null
+++ b/llvm/test/MC/AArch64/SVE2/sqsub-diagnostics.s
@@ -0,0 +1,37 @@
+// RUN: not llvm-mc -triple=aarch64 -show-encoding -mattr=+sve2 2>&1 < %s| FileCheck %s
+
+// --------------------------------------------------------------------------//
+// Source and Destination Registers must match
+
+sqsub z0.b, p0/m, z1.b, z2.b
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: operand must match destination register
+// CHECK-NEXT: sqsub z0.b, p0/m, z1.b, z2.b
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+
+// --------------------------------------------------------------------------//
+// Element sizes must match
+
+sqsub z0.b, p0/m, z0.d, z1.d
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
+// CHECK-NEXT: sqsub z0.b, p0/m, z0.d, z1.d
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+sqsub z0.b, p0/m, z0.b, z1.h
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
+// CHECK-NEXT: sqsub z0.b, p0/m, z0.b, z1.h
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+
+// --------------------------------------------------------------------------//
+// Invalid predicate
+
+sqsub z0.b, p0/z, z0.b, z1.b
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
+// CHECK-NEXT: sqsub z0.b, p0/z, z0.b, z1.b
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+sqsub z0.b, p8/m, z0.b, z1.b
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: restricted predicate has range [0, 7].
+// CHECK-NEXT: sqsub z0.b, p8/m, z0.b, z1.b
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
diff --git a/llvm/test/MC/AArch64/SVE2/sqsub.s b/llvm/test/MC/AArch64/SVE2/sqsub.s
new file mode 100644
index 00000000000..9a3e4c73bfc
--- /dev/null
+++ b/llvm/test/MC/AArch64/SVE2/sqsub.s
@@ -0,0 +1,59 @@
+// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sve2 < %s \
+// RUN:        | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
+// RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \
+// RUN:        | FileCheck %s --check-prefix=CHECK-ERROR
+// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve2 < %s \
+// RUN:        | llvm-objdump -d -mattr=+sve2 - | FileCheck %s --check-prefix=CHECK-INST
+// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve2 < %s \
+// RUN:        | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN
+
+sqsub z0.b, p0/m, z0.b, z1.b
+// CHECK-INST: sqsub z0.b, p0/m, z0.b, z1.b
+// CHECK-ENCODING: [0x20,0x80,0x1a,0x44]
+// CHECK-ERROR: instruction requires: sve2
+// CHECK-UNKNOWN: 20 80 1a 44 <unknown>
+
+sqsub z0.h, p0/m, z0.h, z1.h
+// CHECK-INST: sqsub z0.h, p0/m, z0.h, z1.h
+// CHECK-ENCODING: [0x20,0x80,0x5a,0x44]
+// CHECK-ERROR: instruction requires: sve2
+// CHECK-UNKNOWN: 20 80 5a 44 <unknown>
+
+sqsub z29.s, p7/m, z29.s, z30.s
+// CHECK-INST: sqsub z29.s, p7/m, z29.s, z30.s
+// CHECK-ENCODING: [0xdd,0x9f,0x9a,0x44]
+// CHECK-ERROR: instruction requires: sve2
+// CHECK-UNKNOWN: dd 9f 9a 44 <unknown>
+
+sqsub z31.d, p7/m, z31.d, z30.d
+// CHECK-INST: sqsub z31.d, p7/m, z31.d, z30.d
+// CHECK-ENCODING: [0xdf,0x9f,0xda,0x44]
+// CHECK-ERROR: instruction requires: sve2
+// CHECK-UNKNOWN: df 9f da 44 <unknown>
+
+// --------------------------------------------------------------------------//
+// Test compatibility with MOVPRFX instruction.
+
+movprfx z31.d, p0/z, z6.d
+// CHECK-INST: movprfx z31.d, p0/z, z6.d
+// CHECK-ENCODING: [0xdf,0x20,0xd0,0x04]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: df 20 d0 04 <unknown>
+
+sqsub z31.d, p0/m, z31.d, z30.d
+// CHECK-INST: sqsub z31.d, p0/m, z31.d, z30.d
+// CHECK-ENCODING: [0xdf,0x83,0xda,0x44]
+// CHECK-ERROR: instruction requires: sve2
+// CHECK-UNKNOWN: df 83 da 44 <unknown>
+
+movprfx z31, z6
+// CHECK-INST: movprfx z31, z6
+// CHECK-ENCODING: [0xdf,0xbc,0x20,0x04]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: df bc 20 04 <unknown>
+
+sqsub z31.d, p7/m, z31.d, z30.d
+// CHECK-INST: sqsub z31.d, p7/m, z31.d, z30.d
+// CHECK-ENCODING: [0xdf,0x9f,0xda,0x44]
+// CHECK-ERROR: instruction requires: sve2
+// CHECK-UNKNOWN: df 9f da 44 <unknown>
diff --git a/llvm/test/MC/AArch64/SVE2/sqsubr-diagnostics.s b/llvm/test/MC/AArch64/SVE2/sqsubr-diagnostics.s
new file mode 100644
index 00000000000..af7caaa67ab
--- /dev/null
+++ b/llvm/test/MC/AArch64/SVE2/sqsubr-diagnostics.s
@@ -0,0 +1,37 @@
+// RUN: not llvm-mc -triple=aarch64 -show-encoding -mattr=+sve2 2>&1 < %s| FileCheck %s
+
+// --------------------------------------------------------------------------//
+// Source and Destination Registers must match
+
+sqsubr z0.b, p0/m, z1.b, z2.b
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: operand must match destination register
+// CHECK-NEXT: sqsubr z0.b, p0/m, z1.b, z2.b
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+
+// --------------------------------------------------------------------------//
+// Element sizes must match
+
+sqsubr z0.b, p0/m, z0.d, z1.d
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
+// CHECK-NEXT: sqsubr z0.b, p0/m, z0.d, z1.d
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+sqsubr z0.b, p0/m, z0.b, z1.h
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
+// CHECK-NEXT: sqsubr z0.b, p0/m, z0.b, z1.h
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+
+// --------------------------------------------------------------------------//
+// Invalid predicate
+
+sqsubr z0.b, p0/z, z0.b, z1.b
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
+// CHECK-NEXT: sqsubr z0.b, p0/z, z0.b, z1.b
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+sqsubr z0.b, p8/m, z0.b, z1.b
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: restricted predicate has range [0, 7].
+// CHECK-NEXT: sqsubr z0.b, p8/m, z0.b, z1.b
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
diff --git a/llvm/test/MC/AArch64/SVE2/sqsubr.s b/llvm/test/MC/AArch64/SVE2/sqsubr.s
new file mode 100644
index 00000000000..a19d4fef39e
--- /dev/null
+++ b/llvm/test/MC/AArch64/SVE2/sqsubr.s
@@ -0,0 +1,59 @@
+// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sve2 < %s \
+// RUN:        | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
+// RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \
+// RUN:        | FileCheck %s --check-prefix=CHECK-ERROR
+// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve2 < %s \
+// RUN:        | llvm-objdump -d -mattr=+sve2 - | FileCheck %s --check-prefix=CHECK-INST
+// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve2 < %s \
+// RUN:        | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN
+
+sqsubr z0.b, p0/m, z0.b, z1.b
+// CHECK-INST: sqsubr z0.b, p0/m, z0.b, z1.b
+// CHECK-ENCODING: [0x20,0x80,0x1e,0x44]
+// CHECK-ERROR: instruction requires: sve2
+// CHECK-UNKNOWN: 20 80 1e 44 <unknown>
+
+sqsubr z0.h, p0/m, z0.h, z1.h
+// CHECK-INST: sqsubr z0.h, p0/m, z0.h, z1.h
+// CHECK-ENCODING: [0x20,0x80,0x5e,0x44]
+// CHECK-ERROR: instruction requires: sve2
+// CHECK-UNKNOWN: 20 80 5e 44 <unknown>
+
+sqsubr z29.s, p7/m, z29.s, z30.s
+// CHECK-INST: sqsubr z29.s, p7/m, z29.s, z30.s
+// CHECK-ENCODING: [0xdd,0x9f,0x9e,0x44]
+// CHECK-ERROR: instruction requires: sve2
+// CHECK-UNKNOWN: dd 9f 9e 44 <unknown>
+
+sqsubr z31.d, p7/m, z31.d, z30.d
+// CHECK-INST: sqsubr z31.d, p7/m, z31.d, z30.d
+// CHECK-ENCODING: [0xdf,0x9f,0xde,0x44]
+// CHECK-ERROR: instruction requires: sve2
+// CHECK-UNKNOWN: df 9f de 44 <unknown>
+
+// --------------------------------------------------------------------------//
+// Test compatibility with MOVPRFX instruction.
+
+movprfx z31.d, p0/z, z6.d
+// CHECK-INST: movprfx z31.d, p0/z, z6.d
+// CHECK-ENCODING: [0xdf,0x20,0xd0,0x04]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: df 20 d0 04 <unknown>
+
+sqsubr z31.d, p0/m, z31.d, z30.d
+// CHECK-INST: sqsubr z31.d, p0/m, z31.d, z30.d
+// CHECK-ENCODING: [0xdf,0x83,0xde,0x44]
+// CHECK-ERROR: instruction requires: sve2
+// CHECK-UNKNOWN: df 83 de 44 <unknown>
+
+movprfx z31, z6
+// CHECK-INST: movprfx z31, z6
+// CHECK-ENCODING: [0xdf,0xbc,0x20,0x04]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: df bc 20 04 <unknown>
+
+sqsubr z31.d, p7/m, z31.d, z30.d
+// CHECK-INST: sqsubr z31.d, p7/m, z31.d, z30.d
+// CHECK-ENCODING: [0xdf,0x9f,0xde,0x44]
+// CHECK-ERROR: instruction requires: sve2
+// CHECK-UNKNOWN: df 9f de 44 <unknown>
diff --git a/llvm/test/MC/AArch64/SVE2/suqadd-diagnostics.s b/llvm/test/MC/AArch64/SVE2/suqadd-diagnostics.s
new file mode 100644
index 00000000000..9faa706b69c
--- /dev/null
+++ b/llvm/test/MC/AArch64/SVE2/suqadd-diagnostics.s
@@ -0,0 +1,37 @@
+// RUN: not llvm-mc -triple=aarch64 -show-encoding -mattr=+sve2 2>&1 < %s| FileCheck %s
+
+// --------------------------------------------------------------------------//
+// Source and Destination Registers must match
+
+suqadd z0.b, p0/m, z1.b, z2.b
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: operand must match destination register
+// CHECK-NEXT: suqadd z0.b, p0/m, z1.b, z2.b
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+
+// --------------------------------------------------------------------------//
+// Element sizes must match
+
+suqadd z0.b, p0/m, z0.d, z1.d
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
+// CHECK-NEXT: suqadd z0.b, p0/m, z0.d, z1.d
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+suqadd z0.b, p0/m, z0.b, z1.h
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
+// CHECK-NEXT: suqadd z0.b, p0/m, z0.b, z1.h
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+
+// --------------------------------------------------------------------------//
+// Invalid predicate
+
+suqadd z0.b, p0/z, z0.b, z1.b
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
+// CHECK-NEXT: suqadd z0.b, p0/z, z0.b, z1.b
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+suqadd z0.b, p8/m, z0.b, z1.b
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: restricted predicate has range [0, 7].
+// CHECK-NEXT: suqadd z0.b, p8/m, z0.b, z1.b
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
diff --git a/llvm/test/MC/AArch64/SVE2/suqadd.s b/llvm/test/MC/AArch64/SVE2/suqadd.s
new file mode 100644
index 00000000000..016275da2e0
--- /dev/null
+++ b/llvm/test/MC/AArch64/SVE2/suqadd.s
@@ -0,0 +1,59 @@
+// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sve2 < %s \
+// RUN:        | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
+// RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \
+// RUN:        | FileCheck %s --check-prefix=CHECK-ERROR
+// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve2 < %s \
+// RUN:        | llvm-objdump -d -mattr=+sve2 - | FileCheck %s --check-prefix=CHECK-INST
+// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve2 < %s \
+// RUN:        | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN
+
+suqadd z0.b, p0/m, z0.b, z1.b
+// CHECK-INST: suqadd z0.b, p0/m, z0.b, z1.b
+// CHECK-ENCODING: [0x20,0x80,0x1c,0x44]
+// CHECK-ERROR: instruction requires: sve2
+// CHECK-UNKNOWN: 20 80 1c 44 <unknown>
+
+suqadd z0.h, p0/m, z0.h, z1.h
+// CHECK-INST: suqadd z0.h, p0/m, z0.h, z1.h
+// CHECK-ENCODING: [0x20,0x80,0x5c,0x44]
+// CHECK-ERROR: instruction requires: sve2
+// CHECK-UNKNOWN: 20 80 5c 44 <unknown>
+
+suqadd z29.s, p7/m, z29.s, z30.s
+// CHECK-INST: suqadd z29.s, p7/m, z29.s, z30.s
+// CHECK-ENCODING: [0xdd,0x9f,0x9c,0x44]
+// CHECK-ERROR: instruction requires: sve2
+// CHECK-UNKNOWN: dd 9f 9c 44 <unknown>
+
+suqadd z31.d, p7/m, z31.d, z30.d
+// CHECK-INST: suqadd z31.d, p7/m, z31.d, z30.d
+// CHECK-ENCODING: [0xdf,0x9f,0xdc,0x44]
+// CHECK-ERROR: instruction requires: sve2
+// CHECK-UNKNOWN: df 9f dc 44 <unknown>
+
+// --------------------------------------------------------------------------//
+// Test compatibility with MOVPRFX instruction.
+
+movprfx z31.d, p0/z, z6.d
+// CHECK-INST: movprfx z31.d, p0/z, z6.d
+// CHECK-ENCODING: [0xdf,0x20,0xd0,0x04]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: df 20 d0 04 <unknown>
+
+suqadd z31.d, p0/m, z31.d, z30.d
+// CHECK-INST: suqadd z31.d, p0/m, z31.d, z30.d
+// CHECK-ENCODING: [0xdf,0x83,0xdc,0x44]
+// CHECK-ERROR: instruction requires: sve2
+// CHECK-UNKNOWN: df 83 dc 44 <unknown>
+
+movprfx z31, z6
+// CHECK-INST: movprfx z31, z6
+// CHECK-ENCODING: [0xdf,0xbc,0x20,0x04]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: df bc 20 04 <unknown>
+
+suqadd z31.d, p7/m, z31.d, z30.d
+// CHECK-INST: suqadd z31.d, p7/m, z31.d, z30.d
+// CHECK-ENCODING: [0xdf,0x9f,0xdc,0x44]
+// CHECK-ERROR: instruction requires: sve2
+// CHECK-UNKNOWN: df 9f dc 44 <unknown>
diff --git a/llvm/test/MC/AArch64/SVE2/uqadd-diagnostics.s b/llvm/test/MC/AArch64/SVE2/uqadd-diagnostics.s
new file mode 100644
index 00000000000..c08a0cc4b46
--- /dev/null
+++ b/llvm/test/MC/AArch64/SVE2/uqadd-diagnostics.s
@@ -0,0 +1,37 @@
+// RUN: not llvm-mc -triple=aarch64 -show-encoding -mattr=+sve2 2>&1 < %s| FileCheck %s
+
+// --------------------------------------------------------------------------//
+// Source and Destination Registers must match
+
+uqadd z0.b, p0/m, z1.b, z2.b
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: operand must match destination register
+// CHECK-NEXT: uqadd z0.b, p0/m, z1.b, z2.b
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+
+// --------------------------------------------------------------------------//
+// Element sizes must match
+
+uqadd z0.b, p0/m, z0.d, z1.d
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
+// CHECK-NEXT: uqadd z0.b, p0/m, z0.d, z1.d
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+uqadd z0.b, p0/m, z0.b, z1.h
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
+// CHECK-NEXT: uqadd z0.b, p0/m, z0.b, z1.h
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+
+// --------------------------------------------------------------------------//
+// Invalid predicate
+
+uqadd z0.b, p0/z, z0.b, z1.b
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
+// CHECK-NEXT: uqadd z0.b, p0/z, z0.b, z1.b
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+uqadd z0.b, p8/m, z0.b, z1.b
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: restricted predicate has range [0, 7].
+// CHECK-NEXT: uqadd z0.b, p8/m, z0.b, z1.b
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
diff --git a/llvm/test/MC/AArch64/SVE2/uqadd.s b/llvm/test/MC/AArch64/SVE2/uqadd.s
new file mode 100644
index 00000000000..54d96163994
--- /dev/null
+++ b/llvm/test/MC/AArch64/SVE2/uqadd.s
@@ -0,0 +1,59 @@
+// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sve2 < %s \
+// RUN:        | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
+// RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \
+// RUN:        | FileCheck %s --check-prefix=CHECK-ERROR
+// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve2 < %s \
+// RUN:        | llvm-objdump -d -mattr=+sve2 - | FileCheck %s --check-prefix=CHECK-INST
+// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve2 < %s \
+// RUN:        | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN
+
+uqadd z0.b, p0/m, z0.b, z1.b
+// CHECK-INST: uqadd z0.b, p0/m, z0.b, z1.b
+// CHECK-ENCODING: [0x20,0x80,0x19,0x44]
+// CHECK-ERROR: instruction requires: sve2
+// CHECK-UNKNOWN: 20 80 19 44 <unknown>
+
+uqadd z0.h, p0/m, z0.h, z1.h
+// CHECK-INST: uqadd z0.h, p0/m, z0.h, z1.h
+// CHECK-ENCODING: [0x20,0x80,0x59,0x44]
+// CHECK-ERROR: instruction requires: sve2
+// CHECK-UNKNOWN: 20 80 59 44 <unknown>
+
+uqadd z29.s, p7/m, z29.s, z30.s
+// CHECK-INST: uqadd z29.s, p7/m, z29.s, z30.s
+// CHECK-ENCODING: [0xdd,0x9f,0x99,0x44]
+// CHECK-ERROR: instruction requires: sve2
+// CHECK-UNKNOWN: dd 9f 99 44 <unknown>
+
+uqadd z31.d, p7/m, z31.d, z30.d
+// CHECK-INST: uqadd z31.d, p7/m, z31.d, z30.d
+// CHECK-ENCODING: [0xdf,0x9f,0xd9,0x44]
+// CHECK-ERROR: instruction requires: sve2
+// CHECK-UNKNOWN: df 9f d9 44 <unknown>
+
+// --------------------------------------------------------------------------//
+// Test compatibility with MOVPRFX instruction.
+
+movprfx z31.d, p0/z, z6.d
+// CHECK-INST: movprfx z31.d, p0/z, z6.d
+// CHECK-ENCODING: [0xdf,0x20,0xd0,0x04]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: df 20 d0 04 <unknown>
+
+uqadd z31.d, p0/m, z31.d, z30.d
+// CHECK-INST: uqadd z31.d, p0/m, z31.d, z30.d
+// CHECK-ENCODING: [0xdf,0x83,0xd9,0x44]
+// CHECK-ERROR: instruction requires: sve2
+// CHECK-UNKNOWN: df 83 d9 44 <unknown>
+
+movprfx z31, z6
+// CHECK-INST: movprfx z31, z6
+// CHECK-ENCODING: [0xdf,0xbc,0x20,0x04]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: df bc 20 04 <unknown>
+
+uqadd z31.d, p7/m, z31.d, z30.d
+// CHECK-INST: uqadd z31.d, p7/m, z31.d, z30.d
+// CHECK-ENCODING: [0xdf,0x9f,0xd9,0x44]
+// CHECK-ERROR: instruction requires: sve2
+// CHECK-UNKNOWN: df 9f d9 44 <unknown>
diff --git a/llvm/test/MC/AArch64/SVE2/uqsub-diagnostics.s b/llvm/test/MC/AArch64/SVE2/uqsub-diagnostics.s
new file mode 100644
index 00000000000..486c458d43e
--- /dev/null
+++ b/llvm/test/MC/AArch64/SVE2/uqsub-diagnostics.s
@@ -0,0 +1,37 @@
+// RUN: not llvm-mc -triple=aarch64 -show-encoding -mattr=+sve2 2>&1 < %s| FileCheck %s
+
+// --------------------------------------------------------------------------//
+// Source and Destination Registers must match
+
+uqsub z0.b, p0/m, z1.b, z2.b
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: operand must match destination register
+// CHECK-NEXT: uqsub z0.b, p0/m, z1.b, z2.b
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+
+// --------------------------------------------------------------------------//
+// Element sizes must match
+
+uqsub z0.b, p0/m, z0.d, z1.d
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
+// CHECK-NEXT: uqsub z0.b, p0/m, z0.d, z1.d
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+uqsub z0.b, p0/m, z0.b, z1.h
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
+// CHECK-NEXT: uqsub z0.b, p0/m, z0.b, z1.h
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+
+// --------------------------------------------------------------------------//
+// Invalid predicate
+
+uqsub z0.b, p0/z, z0.b, z1.b
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
+// CHECK-NEXT: uqsub z0.b, p0/z, z0.b, z1.b
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+uqsub z0.b, p8/m, z0.b, z1.b
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: restricted predicate has range [0, 7].
+// CHECK-NEXT: uqsub z0.b, p8/m, z0.b, z1.b
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
diff --git a/llvm/test/MC/AArch64/SVE2/uqsub.s b/llvm/test/MC/AArch64/SVE2/uqsub.s
new file mode 100644
index 00000000000..0df03aa2f30
--- /dev/null
+++ b/llvm/test/MC/AArch64/SVE2/uqsub.s
@@ -0,0 +1,59 @@
+// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sve2 < %s \
+// RUN:        | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
+// RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \
+// RUN:        | FileCheck %s --check-prefix=CHECK-ERROR
+// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve2 < %s \
+// RUN:        | llvm-objdump -d -mattr=+sve2 - | FileCheck %s --check-prefix=CHECK-INST
+// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve2 < %s \
+// RUN:        | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN
+
+uqsub z0.b, p0/m, z0.b, z1.b
+// CHECK-INST: uqsub z0.b, p0/m, z0.b, z1.b
+// CHECK-ENCODING: [0x20,0x80,0x1b,0x44]
+// CHECK-ERROR: instruction requires: sve2
+// CHECK-UNKNOWN: 20 80 1b 44 <unknown>
+
+uqsub z0.h, p0/m, z0.h, z1.h
+// CHECK-INST: uqsub z0.h, p0/m, z0.h, z1.h
+// CHECK-ENCODING: [0x20,0x80,0x5b,0x44]
+// CHECK-ERROR: instruction requires: sve2
+// CHECK-UNKNOWN: 20 80 5b 44 <unknown>
+
+uqsub z29.s, p7/m, z29.s, z30.s
+// CHECK-INST: uqsub z29.s, p7/m, z29.s, z30.s
+// CHECK-ENCODING: [0xdd,0x9f,0x9b,0x44]
+// CHECK-ERROR: instruction requires: sve2
+// CHECK-UNKNOWN: dd 9f 9b 44 <unknown>
+
+uqsub z31.d, p7/m, z31.d, z30.d
+// CHECK-INST: uqsub z31.d, p7/m, z31.d, z30.d
+// CHECK-ENCODING: [0xdf,0x9f,0xdb,0x44]
+// CHECK-ERROR: instruction requires: sve2
+// CHECK-UNKNOWN: df 9f db 44 <unknown>
+
+// --------------------------------------------------------------------------//
+// Test compatibility with MOVPRFX instruction.
+
+movprfx z31.d, p0/z, z6.d
+// CHECK-INST: movprfx z31.d, p0/z, z6.d
+// CHECK-ENCODING: [0xdf,0x20,0xd0,0x04]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: df 20 d0 04 <unknown>
+
+uqsub z31.d, p0/m, z31.d, z30.d
+// CHECK-INST: uqsub z31.d, p0/m, z31.d, z30.d
+// CHECK-ENCODING: [0xdf,0x83,0xdb,0x44]
+// CHECK-ERROR: instruction requires: sve2
+// CHECK-UNKNOWN: df 83 db 44 <unknown>
+
+movprfx z31, z6
+// CHECK-INST: movprfx z31, z6
+// CHECK-ENCODING: [0xdf,0xbc,0x20,0x04]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: df bc 20 04 <unknown>
+
+uqsub z31.d, p7/m, z31.d, z30.d
+// CHECK-INST: uqsub z31.d, p7/m, z31.d, z30.d
+// CHECK-ENCODING: [0xdf,0x9f,0xdb,0x44]
+// CHECK-ERROR: instruction requires: sve2
+// CHECK-UNKNOWN: df 9f db 44 <unknown>
diff --git a/llvm/test/MC/AArch64/SVE2/uqsubr-diagnostics.s b/llvm/test/MC/AArch64/SVE2/uqsubr-diagnostics.s
new file mode 100644
index 00000000000..e6300a2e54b
--- /dev/null
+++ b/llvm/test/MC/AArch64/SVE2/uqsubr-diagnostics.s
@@ -0,0 +1,37 @@
+// RUN: not llvm-mc -triple=aarch64 -show-encoding -mattr=+sve2 2>&1 < %s| FileCheck %s
+
+// --------------------------------------------------------------------------//
+// Source and Destination Registers must match
+
+uqsubr z0.b, p0/m, z1.b, z2.b
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: operand must match destination register
+// CHECK-NEXT: uqsubr z0.b, p0/m, z1.b, z2.b
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+
+// --------------------------------------------------------------------------//
+// Element sizes must match
+
+uqsubr z0.b, p0/m, z0.d, z1.d
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
+// CHECK-NEXT: uqsubr z0.b, p0/m, z0.d, z1.d
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+uqsubr z0.b, p0/m, z0.b, z1.h
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
+// CHECK-NEXT: uqsubr z0.b, p0/m, z0.b, z1.h
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+
+// --------------------------------------------------------------------------//
+// Invalid predicate
+
+uqsubr z0.b, p0/z, z0.b, z1.b
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
+// CHECK-NEXT: uqsubr z0.b, p0/z, z0.b, z1.b
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+uqsubr z0.b, p8/m, z0.b, z1.b
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: restricted predicate has range [0, 7].
+// CHECK-NEXT: uqsubr z0.b, p8/m, z0.b, z1.b
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
diff --git a/llvm/test/MC/AArch64/SVE2/uqsubr.s b/llvm/test/MC/AArch64/SVE2/uqsubr.s
new file mode 100644
index 00000000000..64f95c72d86
--- /dev/null
+++ b/llvm/test/MC/AArch64/SVE2/uqsubr.s
@@ -0,0 +1,59 @@
+// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sve2 < %s \
+// RUN:        | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
+// RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \
+// RUN:        | FileCheck %s --check-prefix=CHECK-ERROR
+// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve2 < %s \
+// RUN:        | llvm-objdump -d -mattr=+sve2 - | FileCheck %s --check-prefix=CHECK-INST
+// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve2 < %s \
+// RUN:        | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN
+
+uqsubr z0.b, p0/m, z0.b, z1.b
+// CHECK-INST: uqsubr z0.b, p0/m, z0.b, z1.b
+// CHECK-ENCODING: [0x20,0x80,0x1f,0x44]
+// CHECK-ERROR: instruction requires: sve2
+// CHECK-UNKNOWN: 20 80 1f 44 <unknown>
+
+uqsubr z0.h, p0/m, z0.h, z1.h
+// CHECK-INST: uqsubr z0.h, p0/m, z0.h, z1.h
+// CHECK-ENCODING: [0x20,0x80,0x5f,0x44]
+// CHECK-ERROR: instruction requires: sve2
+// CHECK-UNKNOWN: 20 80 5f 44 <unknown>
+
+uqsubr z29.s, p7/m, z29.s, z30.s
+// CHECK-INST: uqsubr z29.s, p7/m, z29.s, z30.s
+// CHECK-ENCODING: [0xdd,0x9f,0x9f,0x44]
+// CHECK-ERROR: instruction requires: sve2
+// CHECK-UNKNOWN: dd 9f 9f 44 <unknown>
+
+uqsubr z31.d, p7/m, z31.d, z30.d
+// CHECK-INST: uqsubr z31.d, p7/m, z31.d, z30.d
+// CHECK-ENCODING: [0xdf,0x9f,0xdf,0x44]
+// CHECK-ERROR: instruction requires: sve2
+// CHECK-UNKNOWN: df 9f df 44 <unknown>
+
+// --------------------------------------------------------------------------//
+// Test compatibility with MOVPRFX instruction.
+
+movprfx z31.d, p0/z, z6.d
+// CHECK-INST: movprfx z31.d, p0/z, z6.d
+// CHECK-ENCODING: [0xdf,0x20,0xd0,0x04]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: df 20 d0 04 <unknown>
+
+uqsubr z31.d, p0/m, z31.d, z30.d
+// CHECK-INST: uqsubr z31.d, p0/m, z31.d, z30.d
+// CHECK-ENCODING: [0xdf,0x83,0xdf,0x44]
+// CHECK-ERROR: instruction requires: sve2
+// CHECK-UNKNOWN: df 83 df 44 <unknown>
+
+movprfx z31, z6
+// CHECK-INST: movprfx z31, z6
+// CHECK-ENCODING: [0xdf,0xbc,0x20,0x04]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: df bc 20 04 <unknown>
+
+uqsubr z31.d, p7/m, z31.d, z30.d
+// CHECK-INST: uqsubr z31.d, p7/m, z31.d, z30.d
+// CHECK-ENCODING: [0xdf,0x9f,0xdf,0x44]
+// CHECK-ERROR: instruction requires: sve2
+// CHECK-UNKNOWN: df 9f df 44 <unknown>
diff --git a/llvm/test/MC/AArch64/SVE2/usqadd-diagnostics.s b/llvm/test/MC/AArch64/SVE2/usqadd-diagnostics.s
new file mode 100644
index 00000000000..4c7271f9830
--- /dev/null
+++ b/llvm/test/MC/AArch64/SVE2/usqadd-diagnostics.s
@@ -0,0 +1,37 @@
+// RUN: not llvm-mc -triple=aarch64 -show-encoding -mattr=+sve2 2>&1 < %s| FileCheck %s
+
+// --------------------------------------------------------------------------//
+// Source and Destination Registers must match
+
+usqadd z0.b, p0/m, z1.b, z2.b
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: operand must match destination register
+// CHECK-NEXT: usqadd z0.b, p0/m, z1.b, z2.b
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+
+// --------------------------------------------------------------------------//
+// Element sizes must match
+
+usqadd z0.b, p0/m, z0.d, z1.d
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
+// CHECK-NEXT: usqadd z0.b, p0/m, z0.d, z1.d
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+usqadd z0.b, p0/m, z0.b, z1.h
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
+// CHECK-NEXT: usqadd z0.b, p0/m, z0.b, z1.h
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+
+// --------------------------------------------------------------------------//
+// Invalid predicate
+
+usqadd z0.b, p0/z, z0.b, z1.b
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
+// CHECK-NEXT: usqadd z0.b, p0/z, z0.b, z1.b
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+usqadd z0.b, p8/m, z0.b, z1.b
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: restricted predicate has range [0, 7].
+// CHECK-NEXT: usqadd z0.b, p8/m, z0.b, z1.b
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
diff --git a/llvm/test/MC/AArch64/SVE2/usqadd.s b/llvm/test/MC/AArch64/SVE2/usqadd.s
new file mode 100644
index 00000000000..9bec555dcbd
--- /dev/null
+++ b/llvm/test/MC/AArch64/SVE2/usqadd.s
@@ -0,0 +1,59 @@
+// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sve2 < %s \
+// RUN:        | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
+// RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \
+// RUN:        | FileCheck %s --check-prefix=CHECK-ERROR
+// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve2 < %s \
+// RUN:        | llvm-objdump -d -mattr=+sve2 - | FileCheck %s --check-prefix=CHECK-INST
+// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve2 < %s \
+// RUN:        | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN
+
+usqadd z0.b, p0/m, z0.b, z1.b
+// CHECK-INST: usqadd z0.b, p0/m, z0.b, z1.b
+// CHECK-ENCODING: [0x20,0x80,0x1d,0x44]
+// CHECK-ERROR: instruction requires: sve2
+// CHECK-UNKNOWN: 20 80 1d 44 <unknown>
+
+usqadd z0.h, p0/m, z0.h, z1.h
+// CHECK-INST: usqadd z0.h, p0/m, z0.h, z1.h
+// CHECK-ENCODING: [0x20,0x80,0x5d,0x44]
+// CHECK-ERROR: instruction requires: sve2
+// CHECK-UNKNOWN: 20 80 5d 44 <unknown>
+
+usqadd z29.s, p7/m, z29.s, z30.s
+// CHECK-INST: usqadd z29.s, p7/m, z29.s, z30.s
+// CHECK-ENCODING: [0xdd,0x9f,0x9d,0x44]
+// CHECK-ERROR: instruction requires: sve2
+// CHECK-UNKNOWN: dd 9f 9d 44 <unknown>
+
+usqadd z31.d, p7/m, z31.d, z30.d
+// CHECK-INST: usqadd z31.d, p7/m, z31.d, z30.d
+// CHECK-ENCODING: [0xdf,0x9f,0xdd,0x44]
+// CHECK-ERROR: instruction requires: sve2
+// CHECK-UNKNOWN: df 9f dd 44 <unknown>
+
+// --------------------------------------------------------------------------//
+// Test compatibility with MOVPRFX instruction.
+
+movprfx z31.d, p0/z, z6.d
+// CHECK-INST: movprfx z31.d, p0/z, z6.d
+// CHECK-ENCODING: [0xdf,0x20,0xd0,0x04]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: df 20 d0 04 <unknown>
+
+usqadd z31.d, p0/m, z31.d, z30.d
+// CHECK-INST: usqadd z31.d, p0/m, z31.d, z30.d
+// CHECK-ENCODING: [0xdf,0x83,0xdd,0x44]
+// CHECK-ERROR: instruction requires: sve2
+// CHECK-UNKNOWN: df 83 dd 44 <unknown>
+
+movprfx z31, z6
+// CHECK-INST: movprfx z31, z6
+// CHECK-ENCODING: [0xdf,0xbc,0x20,0x04]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: df bc 20 04 <unknown>
+
+usqadd z31.d, p7/m, z31.d, z30.d
+// CHECK-INST: usqadd z31.d, p7/m, z31.d, z30.d
+// CHECK-ENCODING: [0xdf,0x9f,0xdd,0x44]
+// CHECK-ERROR: instruction requires: sve2
+// CHECK-UNKNOWN: df 9f dd 44 <unknown>