diff options
| -rw-r--r-- | llvm/lib/Target/AMDGPU/AMDGPUSubtarget.cpp | 18 | ||||
| -rw-r--r-- | llvm/lib/Target/AMDGPU/AMDGPUTargetMachine.cpp | 43 | ||||
| -rw-r--r-- | llvm/lib/Target/AMDGPU/InstPrinter/AMDGPUInstPrinter.cpp | 9 | ||||
| -rw-r--r-- | llvm/lib/Target/AMDGPU/MCTargetDesc/R600MCCodeEmitter.cpp | 13 | ||||
| -rw-r--r-- | llvm/lib/Target/AMDGPU/MCTargetDesc/SIMCCodeEmitter.cpp | 27 | ||||
| -rw-r--r-- | llvm/lib/Target/AMDGPU/R600FrameLowering.cpp | 3 | ||||
| -rw-r--r-- | llvm/lib/Target/AMDGPU/R600OptimizeVectorRegisters.cpp | 69 | ||||
| -rw-r--r-- | llvm/lib/Target/AMDGPU/SIMachineScheduler.cpp | 40 | ||||
| -rw-r--r-- | llvm/lib/Target/PowerPC/PPCAsmPrinter.cpp | 45 | ||||
| -rw-r--r-- | llvm/lib/Target/PowerPC/PPCBoolRetToInt.cpp | 60 | ||||
| -rw-r--r-- | llvm/utils/TableGen/InstrInfoEmitter.cpp | 24 |
11 files changed, 206 insertions, 145 deletions
diff --git a/llvm/lib/Target/AMDGPU/AMDGPUSubtarget.cpp b/llvm/lib/Target/AMDGPU/AMDGPUSubtarget.cpp index 6a0275a1317..74851aedbb2 100644 --- a/llvm/lib/Target/AMDGPU/AMDGPUSubtarget.cpp +++ b/llvm/lib/Target/AMDGPU/AMDGPUSubtarget.cpp @@ -13,14 +13,10 @@ //===----------------------------------------------------------------------===// #include "AMDGPUSubtarget.h" -#include "R600ISelLowering.h" -#include "R600InstrInfo.h" -#include "SIFrameLowering.h" -#include "SIISelLowering.h" -#include "SIInstrInfo.h" -#include "SIMachineFunctionInfo.h" #include "llvm/ADT/SmallString.h" #include "llvm/CodeGen/MachineScheduler.h" +#include "llvm/Target/TargetFrameLowering.h" +#include <algorithm> using namespace llvm; @@ -31,7 +27,7 @@ using namespace llvm; #define GET_SUBTARGETINFO_CTOR #include "AMDGPUGenSubtargetInfo.inc" -AMDGPUSubtarget::~AMDGPUSubtarget() {} +AMDGPUSubtarget::~AMDGPUSubtarget() = default; AMDGPUSubtarget & AMDGPUSubtarget::initializeSubtargetDependencies(const Triple &TT, @@ -124,8 +120,7 @@ AMDGPUSubtarget::AMDGPUSubtarget(const Triple &TT, StringRef GPU, StringRef FS, ScalarizeGlobal(false), FeatureDisable(false), - InstrItins(getInstrItineraryForCPU(GPU)), - TSInfo() { + InstrItins(getInstrItineraryForCPU(GPU)) { initializeSubtargetDependencies(TT, GPU, FS); } @@ -189,7 +184,6 @@ unsigned AMDGPUSubtarget::getOccupancyWithLocalMemSize(uint32_t Bytes) const { std::pair<unsigned, unsigned> AMDGPUSubtarget::getFlatWorkGroupSizes( const Function &F) const { - // Default minimum/maximum flat work group sizes. std::pair<unsigned, unsigned> Default = AMDGPU::isCompute(F.getCallingConv()) ? @@ -222,7 +216,6 @@ std::pair<unsigned, unsigned> AMDGPUSubtarget::getFlatWorkGroupSizes( std::pair<unsigned, unsigned> AMDGPUSubtarget::getWavesPerEU( const Function &F) const { - // Default minimum/maximum number of waves per execution unit. std::pair<unsigned, unsigned> Default(1, 0); @@ -281,8 +274,7 @@ SISubtarget::SISubtarget(const Triple &TT, StringRef GPU, StringRef FS, AMDGPUSubtarget(TT, GPU, FS, TM), InstrInfo(*this), FrameLowering(TargetFrameLowering::StackGrowsUp, getStackAlignment(), 0), - TLInfo(TM, *this), - GISel() {} + TLInfo(TM, *this) {} void SISubtarget::overrideSchedPolicy(MachineSchedPolicy &Policy, unsigned NumRegionInstrs) const { diff --git a/llvm/lib/Target/AMDGPU/AMDGPUTargetMachine.cpp b/llvm/lib/Target/AMDGPU/AMDGPUTargetMachine.cpp index 712c5497f45..d8a0c716279 100644 --- a/llvm/lib/Target/AMDGPU/AMDGPUTargetMachine.cpp +++ b/llvm/lib/Target/AMDGPU/AMDGPUTargetMachine.cpp @@ -19,13 +19,15 @@ #include "AMDGPUTargetObjectFile.h" #include "AMDGPUTargetTransformInfo.h" #include "GCNSchedStrategy.h" -#include "R600ISelLowering.h" -#include "R600InstrInfo.h" #include "R600MachineScheduler.h" -#include "SIISelLowering.h" -#include "SIInstrInfo.h" #include "SIMachineScheduler.h" +#include "llvm/ADT/SmallString.h" +#include "llvm/ADT/STLExtras.h" +#include "llvm/ADT/StringRef.h" +#include "llvm/ADT/Triple.h" +#include "llvm/CodeGen/GlobalISel/GISelAccessor.h" #include "llvm/CodeGen/GlobalISel/IRTranslator.h" +#include "llvm/CodeGen/MachineScheduler.h" #include "llvm/CodeGen/Passes.h" #include "llvm/CodeGen/TargetPassConfig.h" #include "llvm/Support/TargetRegistry.h" @@ -34,7 +36,14 @@ #include "llvm/Transforms/Scalar.h" #include "llvm/Transforms/Scalar/GVN.h" #include "llvm/Transforms/Vectorize.h" +#include "llvm/IR/Attributes.h" +#include "llvm/IR/Function.h" #include "llvm/IR/LegacyPassManager.h" +#include "llvm/Pass.h" +#include "llvm/Support/CommandLine.h" +#include "llvm/Support/Compiler.h" +#include "llvm/Target/TargetLoweringObjectFile.h" +#include <memory> using namespace llvm; @@ -69,7 +78,6 @@ static cl::opt<bool> ScalarizeGlobal( cl::init(false), cl::Hidden); - extern "C" void LLVMInitializeAMDGPUTarget() { // Register the target RegisterTargetMachine<R600TargetMachine> X(getTheAMDGPUTarget()); @@ -97,11 +105,11 @@ extern "C" void LLVMInitializeAMDGPUTarget() { } static std::unique_ptr<TargetLoweringObjectFile> createTLOF(const Triple &TT) { - return make_unique<AMDGPUTargetObjectFile>(); + return llvm::make_unique<AMDGPUTargetObjectFile>(); } static ScheduleDAGInstrs *createR600MachineScheduler(MachineSchedContext *C) { - return new ScheduleDAGMILive(C, make_unique<R600SchedStrategy>()); + return new ScheduleDAGMILive(C, llvm::make_unique<R600SchedStrategy>()); } static ScheduleDAGInstrs *createSIMachineScheduler(MachineSchedContext *C) { @@ -111,7 +119,8 @@ static ScheduleDAGInstrs *createSIMachineScheduler(MachineSchedContext *C) { static ScheduleDAGInstrs * createGCNMaxOccupancyMachineScheduler(MachineSchedContext *C) { ScheduleDAGMILive *DAG = - new ScheduleDAGMILive(C, make_unique<GCNMaxOccupancySchedStrategy>(C)); + new ScheduleDAGMILive(C, + llvm::make_unique<GCNMaxOccupancySchedStrategy>(C)); DAG->addMutation(createLoadClusterDAGMutation(DAG->TII, DAG->TRI)); DAG->addMutation(createStoreClusterDAGMutation(DAG->TII, DAG->TRI)); return DAG; @@ -170,12 +179,11 @@ AMDGPUTargetMachine::AMDGPUTargetMachine(const Target &T, const Triple &TT, CodeGenOpt::Level OptLevel) : LLVMTargetMachine(T, computeDataLayout(TT), TT, getGPUOrDefault(TT, CPU), FS, Options, getEffectiveRelocModel(RM), CM, OptLevel), - TLOF(createTLOF(getTargetTriple())), - IntrinsicInfo() { + TLOF(createTLOF(getTargetTriple())) { initAsmInfo(); } -AMDGPUTargetMachine::~AMDGPUTargetMachine() { } +AMDGPUTargetMachine::~AMDGPUTargetMachine() = default; StringRef AMDGPUTargetMachine::getGPUName(const Function &F) const { Attribute GPUAttr = F.getFnAttribute("target-cpu"); @@ -192,7 +200,7 @@ StringRef AMDGPUTargetMachine::getFeatureString(const Function &F) const { } void AMDGPUTargetMachine::addEarlyAsPossiblePasses(PassManagerBase &PM) { - PM.add(llvm::createAMDGPUUnifyMetadataPass()); + PM.add(createAMDGPUUnifyMetadataPass()); } //===----------------------------------------------------------------------===// @@ -234,13 +242,15 @@ const R600Subtarget *R600TargetMachine::getSubtargetImpl( #ifdef LLVM_BUILD_GLOBAL_ISEL namespace { + struct SIGISelActualAccessor : public GISelAccessor { std::unique_ptr<AMDGPUCallLowering> CallLoweringInfo; const AMDGPUCallLowering *getCallLowering() const override { return CallLoweringInfo.get(); } }; -} // End anonymous namespace. + +} // end anonymous namespace #endif GCNTargetMachine::GCNTargetMachine(const Target &T, const Triple &TT, @@ -291,7 +301,6 @@ class AMDGPUPassConfig : public TargetPassConfig { public: AMDGPUPassConfig(TargetMachine *TM, PassManagerBase &PM) : TargetPassConfig(TM, PM) { - // Exceptions and StackMaps are not supported, so these passes will never do // anything. disablePass(&StackMapLivenessID); @@ -322,7 +331,7 @@ public: class R600PassConfig final : public AMDGPUPassConfig { public: R600PassConfig(TargetMachine *TM, PassManagerBase &PM) - : AMDGPUPassConfig(TM, PM) { } + : AMDGPUPassConfig(TM, PM) {} ScheduleDAGInstrs *createMachineScheduler( MachineSchedContext *C) const override { @@ -338,7 +347,7 @@ public: class GCNPassConfig final : public AMDGPUPassConfig { public: GCNPassConfig(TargetMachine *TM, PassManagerBase &PM) - : AMDGPUPassConfig(TM, PM) { } + : AMDGPUPassConfig(TM, PM) {} GCNTargetMachine &getGCNTargetMachine() const { return getTM<GCNTargetMachine>(); @@ -365,7 +374,7 @@ public: void addPreEmitPass() override; }; -} // End of anonymous namespace +} // end anonymous namespace TargetIRAnalysis AMDGPUTargetMachine::getTargetIRAnalysis() { return TargetIRAnalysis([this](const Function &F) { diff --git a/llvm/lib/Target/AMDGPU/InstPrinter/AMDGPUInstPrinter.cpp b/llvm/lib/Target/AMDGPU/InstPrinter/AMDGPUInstPrinter.cpp index b84aaaef090..fb51cb899e1 100644 --- a/llvm/lib/Target/AMDGPU/InstPrinter/AMDGPUInstPrinter.cpp +++ b/llvm/lib/Target/AMDGPU/InstPrinter/AMDGPUInstPrinter.cpp @@ -15,13 +15,14 @@ #include "Utils/AMDGPUBaseInfo.h" #include "llvm/MC/MCExpr.h" #include "llvm/MC/MCInst.h" +#include "llvm/MC/MCInstrDesc.h" #include "llvm/MC/MCInstrInfo.h" #include "llvm/MC/MCRegisterInfo.h" #include "llvm/MC/MCSubtargetInfo.h" +#include "llvm/Support/ErrorHandling.h" #include "llvm/Support/MathExtras.h" #include "llvm/Support/raw_ostream.h" - -#include <string> +#include <cassert> using namespace llvm; using namespace llvm::AMDGPU; @@ -450,7 +451,6 @@ void AMDGPUInstPrinter::printImmediate64(uint64_t Imm, void AMDGPUInstPrinter::printOperand(const MCInst *MI, unsigned OpNo, const MCSubtargetInfo &STI, raw_ostream &O) { - if (OpNo >= MI->getNumOperands()) { O << "/*Missing OP" << OpNo << "*/"; return; @@ -940,7 +940,6 @@ void AMDGPUInstPrinter::printBankSwizzle(const MCInst *MI, unsigned OpNo, default: break; } - return; } void AMDGPUInstPrinter::printRSel(const MCInst *MI, unsigned OpNo, @@ -1037,7 +1036,7 @@ void AMDGPUInstPrinter::printSendMsg(const MCInst *MI, unsigned OpNo, O << "sendmsg(" << IdSymbolic[Id] << ", " << OpSysSymbolic[OpSys] << ')'; return; } - } while (0); + } while (false); O << SImm16; // Unknown simm16 code. } diff --git a/llvm/lib/Target/AMDGPU/MCTargetDesc/R600MCCodeEmitter.cpp b/llvm/lib/Target/AMDGPU/MCTargetDesc/R600MCCodeEmitter.cpp index 43a2136dada..6015ec190fd 100644 --- a/llvm/lib/Target/AMDGPU/MCTargetDesc/R600MCCodeEmitter.cpp +++ b/llvm/lib/Target/AMDGPU/MCTargetDesc/R600MCCodeEmitter.cpp @@ -20,25 +20,30 @@ #include "MCTargetDesc/AMDGPUMCTargetDesc.h" #include "llvm/MC/MCCodeEmitter.h" #include "llvm/MC/MCContext.h" +#include "llvm/MC/MCFixup.h" #include "llvm/MC/MCInst.h" +#include "llvm/MC/MCInstrDesc.h" #include "llvm/MC/MCInstrInfo.h" #include "llvm/MC/MCRegisterInfo.h" #include "llvm/MC/MCSubtargetInfo.h" +#include "llvm/Support/Endian.h" #include "llvm/Support/EndianStream.h" #include "llvm/Support/raw_ostream.h" +#include <cassert> +#include <cstdint> using namespace llvm; namespace { class R600MCCodeEmitter : public AMDGPUMCCodeEmitter { - R600MCCodeEmitter(const R600MCCodeEmitter &) = delete; - void operator=(const R600MCCodeEmitter &) = delete; const MCRegisterInfo &MRI; public: R600MCCodeEmitter(const MCInstrInfo &mcii, const MCRegisterInfo &mri) - : AMDGPUMCCodeEmitter(mcii), MRI(mri) { } + : AMDGPUMCCodeEmitter(mcii), MRI(mri) {} + R600MCCodeEmitter(const R600MCCodeEmitter &) = delete; + R600MCCodeEmitter &operator=(const R600MCCodeEmitter &) = delete; /// \brief Encode the instruction and write it to the OS. void encodeInstruction(const MCInst &MI, raw_ostream &OS, @@ -57,7 +62,7 @@ private: unsigned getHWReg(unsigned regNo) const; }; -} // End anonymous namespace +} // end anonymous namespace enum RegElement { ELEMENT_X = 0, diff --git a/llvm/lib/Target/AMDGPU/MCTargetDesc/SIMCCodeEmitter.cpp b/llvm/lib/Target/AMDGPU/MCTargetDesc/SIMCCodeEmitter.cpp index 4a046acfabb..0c5bb0648a1 100644 --- a/llvm/lib/Target/AMDGPU/MCTargetDesc/SIMCCodeEmitter.cpp +++ b/llvm/lib/Target/AMDGPU/MCTargetDesc/SIMCCodeEmitter.cpp @@ -1,4 +1,4 @@ -//===-- SIMCCodeEmitter.cpp - SI Code Emitter -------------------------------===// +//===-- SIMCCodeEmitter.cpp - SI Code Emitter -----------------------------===// // // The LLVM Compiler Infrastructure // @@ -17,25 +17,30 @@ #include "MCTargetDesc/AMDGPUFixupKinds.h" #include "MCTargetDesc/AMDGPUMCCodeEmitter.h" #include "MCTargetDesc/AMDGPUMCTargetDesc.h" -#include "SIDefines.h" #include "Utils/AMDGPUBaseInfo.h" #include "llvm/MC/MCCodeEmitter.h" #include "llvm/MC/MCContext.h" +#include "llvm/MC/MCExpr.h" #include "llvm/MC/MCFixup.h" #include "llvm/MC/MCInst.h" +#include "llvm/MC/MCInstrDesc.h" #include "llvm/MC/MCInstrInfo.h" #include "llvm/MC/MCRegisterInfo.h" #include "llvm/MC/MCSubtargetInfo.h" #include "llvm/MC/MCSymbol.h" +#include "llvm/Support/Casting.h" +#include "llvm/Support/ErrorHandling.h" +#include "llvm/Support/MathExtras.h" #include "llvm/Support/raw_ostream.h" +#include <cassert> +#include <cstdint> +#include <cstdlib> using namespace llvm; namespace { class SIMCCodeEmitter : public AMDGPUMCCodeEmitter { - SIMCCodeEmitter(const SIMCCodeEmitter &) = delete; - void operator=(const SIMCCodeEmitter &) = delete; const MCRegisterInfo &MRI; /// \brief Encode an fp or int literal @@ -46,8 +51,8 @@ public: SIMCCodeEmitter(const MCInstrInfo &mcii, const MCRegisterInfo &mri, MCContext &ctx) : AMDGPUMCCodeEmitter(mcii), MRI(mri) {} - - ~SIMCCodeEmitter() override {} + SIMCCodeEmitter(const SIMCCodeEmitter &) = delete; + SIMCCodeEmitter &operator=(const SIMCCodeEmitter &) = delete; /// \brief Encode the instruction and write it to the OS. void encodeInstruction(const MCInst &MI, raw_ostream &OS, @@ -66,7 +71,7 @@ public: const MCSubtargetInfo &STI) const override; }; -} // End anonymous namespace +} // end anonymous namespace MCCodeEmitter *llvm::createSIMCCodeEmitter(const MCInstrInfo &MCII, const MCRegisterInfo &MRI, @@ -198,10 +203,9 @@ static uint32_t getLit64Encoding(uint64_t Val, const MCSubtargetInfo &STI) { uint32_t SIMCCodeEmitter::getLitEncoding(const MCOperand &MO, const MCOperandInfo &OpInfo, const MCSubtargetInfo &STI) const { - int64_t Imm; if (MO.isExpr()) { - const MCConstantExpr *C = dyn_cast<MCConstantExpr>(MO.getExpr()); + const auto *C = dyn_cast<MCConstantExpr>(MO.getExpr()); if (!C) return 255; @@ -263,7 +267,7 @@ void SIMCCodeEmitter::encodeInstruction(const MCInst &MI, raw_ostream &OS, if (Op.isImm()) Imm = Op.getImm(); else if (Op.isExpr()) { - if (const MCConstantExpr *C = dyn_cast<MCConstantExpr>(Op.getExpr())) + if (const auto *C = dyn_cast<MCConstantExpr>(Op.getExpr())) Imm = C->getValue(); } else if (!Op.isExpr()) // Exprs will be replaced with a fixup value. @@ -301,7 +305,7 @@ uint64_t SIMCCodeEmitter::getMachineOpValue(const MCInst &MI, return MRI.getEncodingValue(MO.getReg()); if (MO.isExpr() && MO.getExpr()->getKind() != MCExpr::Constant) { - const MCSymbolRefExpr *Expr = dyn_cast<MCSymbolRefExpr>(MO.getExpr()); + const auto *Expr = dyn_cast<MCSymbolRefExpr>(MO.getExpr()); MCFixupKind Kind; if (Expr && Expr->getSymbol().isExternal()) Kind = FK_Data_4; @@ -329,4 +333,3 @@ uint64_t SIMCCodeEmitter::getMachineOpValue(const MCInst &MI, llvm_unreachable("Encoding of this operand type is not supported yet."); return 0; } - diff --git a/llvm/lib/Target/AMDGPU/R600FrameLowering.cpp b/llvm/lib/Target/AMDGPU/R600FrameLowering.cpp index dd5681ff5e8..5813786abe0 100644 --- a/llvm/lib/Target/AMDGPU/R600FrameLowering.cpp +++ b/llvm/lib/Target/AMDGPU/R600FrameLowering.cpp @@ -11,5 +11,4 @@ using namespace llvm; -R600FrameLowering::~R600FrameLowering() { -} +R600FrameLowering::~R600FrameLowering() = default; diff --git a/llvm/lib/Target/AMDGPU/R600OptimizeVectorRegisters.cpp b/llvm/lib/Target/AMDGPU/R600OptimizeVectorRegisters.cpp index 58d4bed3b58..d90008a550a 100644 --- a/llvm/lib/Target/AMDGPU/R600OptimizeVectorRegisters.cpp +++ b/llvm/lib/Target/AMDGPU/R600OptimizeVectorRegisters.cpp @@ -31,22 +31,31 @@ #include "AMDGPUSubtarget.h" #include "R600Defines.h" #include "R600InstrInfo.h" -#include "llvm/CodeGen/DFAPacketizer.h" +#include "llvm/ADT/DenseMap.h" +#include "llvm/ADT/STLExtras.h" +#include "llvm/ADT/StringRef.h" +#include "llvm/CodeGen/MachineBasicBlock.h" #include "llvm/CodeGen/MachineDominators.h" +#include "llvm/CodeGen/MachineFunction.h" #include "llvm/CodeGen/MachineFunctionPass.h" +#include "llvm/CodeGen/MachineInstr.h" #include "llvm/CodeGen/MachineInstrBuilder.h" #include "llvm/CodeGen/MachineLoopInfo.h" +#include "llvm/CodeGen/MachineOperand.h" #include "llvm/CodeGen/MachineRegisterInfo.h" -#include "llvm/CodeGen/Passes.h" +#include "llvm/IR/DebugLoc.h" +#include "llvm/PassAnalysisSupport.h" #include "llvm/Support/Debug.h" +#include "llvm/Support/ErrorHandling.h" #include "llvm/Support/raw_ostream.h" +#include <cassert> +#include <utility> +#include <vector> using namespace llvm; #define DEBUG_TYPE "vec-merger" -namespace { - static bool isImplicitlyDef(MachineRegisterInfo &MRI, unsigned Reg) { for (MachineRegisterInfo::def_instr_iterator It = MRI.def_instr_begin(Reg), @@ -60,11 +69,14 @@ isImplicitlyDef(MachineRegisterInfo &MRI, unsigned Reg) { return false; } +namespace { + class RegSeqInfo { public: MachineInstr *Instr; DenseMap<unsigned, unsigned> RegToChan; std::vector<unsigned> UndefReg; + RegSeqInfo(MachineRegisterInfo &MRI, MachineInstr *MI) : Instr(MI) { assert(MI->getOpcode() == AMDGPU::REG_SEQUENCE); for (unsigned i = 1, e = Instr->getNumOperands(); i < e; i+=2) { @@ -76,7 +88,8 @@ public: RegToChan[MO.getReg()] = Chan; } } - RegSeqInfo() {} + + RegSeqInfo() = default; bool operator==(const RegSeqInfo &RSI) const { return RSI.Instr == Instr; @@ -87,28 +100,30 @@ class R600VectorRegMerger : public MachineFunctionPass { private: MachineRegisterInfo *MRI; const R600InstrInfo *TII; - bool canSwizzle(const MachineInstr &) const; + + bool canSwizzle(const MachineInstr &MI) const; bool areAllUsesSwizzeable(unsigned Reg) const; void SwizzleInput(MachineInstr &, - const std::vector<std::pair<unsigned, unsigned> > &) const; - bool tryMergeVector(const RegSeqInfo *, RegSeqInfo *, - std::vector<std::pair<unsigned, unsigned> > &Remap) const; + const std::vector<std::pair<unsigned, unsigned>> &RemapChan) const; + bool tryMergeVector(const RegSeqInfo *Untouched, RegSeqInfo *ToMerge, + std::vector<std::pair<unsigned, unsigned>> &Remap) const; bool tryMergeUsingCommonSlot(RegSeqInfo &RSI, RegSeqInfo &CompatibleRSI, - std::vector<std::pair<unsigned, unsigned> > &RemapChan); + std::vector<std::pair<unsigned, unsigned>> &RemapChan); bool tryMergeUsingFreeSlot(RegSeqInfo &RSI, RegSeqInfo &CompatibleRSI, - std::vector<std::pair<unsigned, unsigned> > &RemapChan); - MachineInstr *RebuildVector(RegSeqInfo *MI, - const RegSeqInfo *BaseVec, - const std::vector<std::pair<unsigned, unsigned> > &RemapChan) const; + std::vector<std::pair<unsigned, unsigned>> &RemapChan); + MachineInstr *RebuildVector(RegSeqInfo *MI, const RegSeqInfo *BaseVec, + const std::vector<std::pair<unsigned, unsigned>> &RemapChan) const; void RemoveMI(MachineInstr *); void trackRSI(const RegSeqInfo &RSI); - typedef DenseMap<unsigned, std::vector<MachineInstr *> > InstructionSetMap; + typedef DenseMap<unsigned, std::vector<MachineInstr *>> InstructionSetMap; DenseMap<MachineInstr *, RegSeqInfo> PreviousRegSeq; InstructionSetMap PreviousRegSeqByReg; InstructionSetMap PreviousRegSeqByUndefCount; + public: static char ID; + R600VectorRegMerger(TargetMachine &tm) : MachineFunctionPass(ID), TII(nullptr) { } @@ -128,6 +143,8 @@ public: bool runOnMachineFunction(MachineFunction &Fn) override; }; +} // end anonymous namespace. + char R600VectorRegMerger::ID = 0; bool R600VectorRegMerger::canSwizzle(const MachineInstr &MI) @@ -144,7 +161,7 @@ bool R600VectorRegMerger::canSwizzle(const MachineInstr &MI) } bool R600VectorRegMerger::tryMergeVector(const RegSeqInfo *Untouched, - RegSeqInfo *ToMerge, std::vector< std::pair<unsigned, unsigned> > &Remap) + RegSeqInfo *ToMerge, std::vector< std::pair<unsigned, unsigned>> &Remap) const { unsigned CurrentUndexIdx = 0; for (DenseMap<unsigned, unsigned>::iterator It = ToMerge->RegToChan.begin(), @@ -167,7 +184,7 @@ bool R600VectorRegMerger::tryMergeVector(const RegSeqInfo *Untouched, static unsigned getReassignedChan( - const std::vector<std::pair<unsigned, unsigned> > &RemapChan, + const std::vector<std::pair<unsigned, unsigned>> &RemapChan, unsigned Chan) { for (unsigned j = 0, je = RemapChan.size(); j < je; j++) { if (RemapChan[j].first == Chan) @@ -178,7 +195,7 @@ unsigned getReassignedChan( MachineInstr *R600VectorRegMerger::RebuildVector( RegSeqInfo *RSI, const RegSeqInfo *BaseRSI, - const std::vector<std::pair<unsigned, unsigned> > &RemapChan) const { + const std::vector<std::pair<unsigned, unsigned>> &RemapChan) const { unsigned Reg = RSI->Instr->getOperand(0).getReg(); MachineBasicBlock::iterator Pos = RSI->Instr; MachineBasicBlock &MBB = *Pos->getParent(); @@ -200,7 +217,7 @@ MachineInstr *R600VectorRegMerger::RebuildVector( .addReg(SubReg) .addImm(Chan); UpdatedRegToChan[SubReg] = Chan; - std::vector<unsigned>::iterator ChanPos = find(UpdatedUndef, Chan); + std::vector<unsigned>::iterator ChanPos = llvm::find(UpdatedUndef, Chan); if (ChanPos != UpdatedUndef.end()) UpdatedUndef.erase(ChanPos); assert(!is_contained(UpdatedUndef, Chan) && @@ -234,17 +251,17 @@ void R600VectorRegMerger::RemoveMI(MachineInstr *MI) { for (InstructionSetMap::iterator It = PreviousRegSeqByReg.begin(), E = PreviousRegSeqByReg.end(); It != E; ++It) { std::vector<MachineInstr *> &MIs = (*It).second; - MIs.erase(find(MIs, MI), MIs.end()); + MIs.erase(llvm::find(MIs, MI), MIs.end()); } for (InstructionSetMap::iterator It = PreviousRegSeqByUndefCount.begin(), E = PreviousRegSeqByUndefCount.end(); It != E; ++It) { std::vector<MachineInstr *> &MIs = (*It).second; - MIs.erase(find(MIs, MI), MIs.end()); + MIs.erase(llvm::find(MIs, MI), MIs.end()); } } void R600VectorRegMerger::SwizzleInput(MachineInstr &MI, - const std::vector<std::pair<unsigned, unsigned> > &RemapChan) const { + const std::vector<std::pair<unsigned, unsigned>> &RemapChan) const { unsigned Offset; if (TII->get(MI.getOpcode()).TSFlags & R600_InstFlag::TEX_INST) Offset = 2; @@ -272,7 +289,7 @@ bool R600VectorRegMerger::areAllUsesSwizzeable(unsigned Reg) const { bool R600VectorRegMerger::tryMergeUsingCommonSlot(RegSeqInfo &RSI, RegSeqInfo &CompatibleRSI, - std::vector<std::pair<unsigned, unsigned> > &RemapChan) { + std::vector<std::pair<unsigned, unsigned>> &RemapChan) { for (MachineInstr::mop_iterator MOp = RSI.Instr->operands_begin(), MOE = RSI.Instr->operands_end(); MOp != MOE; ++MOp) { if (!MOp->isReg()) @@ -292,7 +309,7 @@ bool R600VectorRegMerger::tryMergeUsingCommonSlot(RegSeqInfo &RSI, bool R600VectorRegMerger::tryMergeUsingFreeSlot(RegSeqInfo &RSI, RegSeqInfo &CompatibleRSI, - std::vector<std::pair<unsigned, unsigned> > &RemapChan) { + std::vector<std::pair<unsigned, unsigned>> &RemapChan) { unsigned NeededUndefs = 4 - RSI.UndefReg.size(); if (PreviousRegSeqByUndefCount[NeededUndefs].empty()) return false; @@ -355,7 +372,7 @@ bool R600VectorRegMerger::runOnMachineFunction(MachineFunction &Fn) { }); RegSeqInfo CandidateRSI; - std::vector<std::pair<unsigned, unsigned> > RemapChan; + std::vector<std::pair<unsigned, unsigned>> RemapChan; DEBUG(dbgs() << "Using common slots...\n";); if (tryMergeUsingCommonSlot(RSI, CandidateRSI, RemapChan)) { // Remove CandidateRSI mapping @@ -379,8 +396,6 @@ bool R600VectorRegMerger::runOnMachineFunction(MachineFunction &Fn) { return false; } -} - llvm::FunctionPass *llvm::createR600VectorRegMerger(TargetMachine &tm) { return new R600VectorRegMerger(tm); } diff --git a/llvm/lib/Target/AMDGPU/SIMachineScheduler.cpp b/llvm/lib/Target/AMDGPU/SIMachineScheduler.cpp index c87d2008a34..b867aff3705 100644 --- a/llvm/lib/Target/AMDGPU/SIMachineScheduler.cpp +++ b/llvm/lib/Target/AMDGPU/SIMachineScheduler.cpp @@ -1,4 +1,4 @@ -//===-- SIMachineScheduler.cpp - SI Scheduler Interface -*- C++ -*-----===// +//===-- SIMachineScheduler.cpp - SI Scheduler Interface -------------------===// // // The LLVM Compiler Infrastructure // @@ -13,12 +13,28 @@ //===----------------------------------------------------------------------===// #include "AMDGPU.h" +#include "SIInstrInfo.h" #include "SIMachineScheduler.h" +#include "SIRegisterInfo.h" +#include "llvm/ADT/STLExtras.h" +#include "llvm/ADT/SmallVector.h" #include "llvm/CodeGen/LiveInterval.h" #include "llvm/CodeGen/LiveIntervalAnalysis.h" +#include "llvm/CodeGen/MachineInstr.h" #include "llvm/CodeGen/MachineRegisterInfo.h" #include "llvm/CodeGen/MachineScheduler.h" #include "llvm/CodeGen/RegisterPressure.h" +#include "llvm/CodeGen/SlotIndexes.h" +#include "llvm/Support/Debug.h" +#include "llvm/Support/ErrorHandling.h" +#include "llvm/Support/raw_ostream.h" +#include "llvm/Target/TargetRegisterInfo.h" +#include <algorithm> +#include <cassert> +#include <map> +#include <set> +#include <utility> +#include <vector> using namespace llvm; @@ -120,7 +136,6 @@ using namespace llvm; // 300-600 cycles. We do not specially take that into account when scheduling // As we expect the driver to be able to preload the constants soon. - // common code // #ifndef NDEBUG @@ -181,7 +196,6 @@ void SIScheduleBlock::addUnit(SUnit *SU) { } #ifndef NDEBUG - void SIScheduleBlock::traceCandidate(const SISchedCandidate &Cand) { dbgs() << " SU(" << Cand.SU->NodeNum << ") " << getReasonStr(Cand.Reason); @@ -479,7 +493,7 @@ void SIScheduleBlock::releaseSuccessors(SUnit *SU, bool InOrOutBlock) { void SIScheduleBlock::nodeScheduled(SUnit *SU) { // Is in TopReadySUs assert (!SU->NumPredsLeft); - std::vector<SUnit *>::iterator I = find(TopReadySUs, SU); + std::vector<SUnit *>::iterator I = llvm::find(TopReadySUs, SU); if (I == TopReadySUs.end()) { dbgs() << "Data Structure Bug in SI Scheduler\n"; llvm_unreachable(nullptr); @@ -588,9 +602,8 @@ void SIScheduleBlock::printDebug(bool full) { } } - dbgs() << "///////////////////////\n"; + dbgs() << "///////////////////////\n"; } - #endif // SIScheduleBlockCreator // @@ -599,8 +612,7 @@ SIScheduleBlockCreator::SIScheduleBlockCreator(SIScheduleDAGMI *DAG) : DAG(DAG) { } -SIScheduleBlockCreator::~SIScheduleBlockCreator() { -} +SIScheduleBlockCreator::~SIScheduleBlockCreator() = default; SIScheduleBlocks SIScheduleBlockCreator::getBlocks(SISchedulerBlockCreatorVariant BlockVariant) { @@ -1058,8 +1070,7 @@ void SIScheduleBlockCreator::createBlocksForVariant(SISchedulerBlockCreatorVaria unsigned Color = CurrentColoring[SU->NodeNum]; if (RealID.find(Color) == RealID.end()) { int ID = CurrentBlocks.size(); - BlockPtrs.push_back( - make_unique<SIScheduleBlock>(DAG, this, ID)); + BlockPtrs.push_back(llvm::make_unique<SIScheduleBlock>(DAG, this, ID)); CurrentBlocks.push_back(BlockPtrs.rbegin()->get()); RealID[Color] = ID; } @@ -1264,7 +1275,7 @@ void SIScheduleBlockCreator::fillStats() { for (unsigned i = 0, e = DAGSize; i != e; ++i) { int BlockIndice = TopDownIndex2Block[i]; SIScheduleBlock *Block = CurrentBlocks[BlockIndice]; - if (Block->getPreds().size() == 0) + if (Block->getPreds().empty()) Block->Depth = 0; else { unsigned Depth = 0; @@ -1279,7 +1290,7 @@ void SIScheduleBlockCreator::fillStats() { for (unsigned i = 0, e = DAGSize; i != e; ++i) { int BlockIndice = BottomUpIndex2Block[i]; SIScheduleBlock *Block = CurrentBlocks[BlockIndice]; - if (Block->getSuccs().size() == 0) + if (Block->getSuccs().empty()) Block->Height = 0; else { unsigned Height = 0; @@ -1653,7 +1664,7 @@ SIScheduler::scheduleVariant(SISchedulerBlockCreatorVariant BlockVariant, // SIScheduleDAGMI // SIScheduleDAGMI::SIScheduleDAGMI(MachineSchedContext *C) : - ScheduleDAGMILive(C, make_unique<GenericScheduler>(C)) { + ScheduleDAGMILive(C, llvm::make_unique<GenericScheduler>(C)) { SITII = static_cast<const SIInstrInfo*>(TII); SITRI = static_cast<const SIRegisterInfo*>(TRI); @@ -1661,8 +1672,7 @@ SIScheduleDAGMI::SIScheduleDAGMI(MachineSchedContext *C) : SGPRSetID = SITRI->getSGPRPressureSet(); } -SIScheduleDAGMI::~SIScheduleDAGMI() { -} +SIScheduleDAGMI::~SIScheduleDAGMI() = default; // Code adapted from scheduleDAG.cpp // Does a topological sort over the SUs. diff --git a/llvm/lib/Target/PowerPC/PPCAsmPrinter.cpp b/llvm/lib/Target/PowerPC/PPCAsmPrinter.cpp index 81e2132c5db..f0e0ebc4946 100644 --- a/llvm/lib/Target/PowerPC/PPCAsmPrinter.cpp +++ b/llvm/lib/Target/PowerPC/PPCAsmPrinter.cpp @@ -17,28 +17,29 @@ //===----------------------------------------------------------------------===// #include "PPC.h" +#include "PPCInstrInfo.h" #include "InstPrinter/PPCInstPrinter.h" #include "MCTargetDesc/PPCMCExpr.h" -#include "MCTargetDesc/PPCPredicates.h" +#include "MCTargetDesc/PPCMCTargetDesc.h" #include "PPCMachineFunctionInfo.h" #include "PPCSubtarget.h" #include "PPCTargetMachine.h" #include "PPCTargetStreamer.h" #include "llvm/ADT/MapVector.h" -#include "llvm/ADT/StringExtras.h" +#include "llvm/ADT/StringRef.h" +#include "llvm/ADT/Triple.h" +#include "llvm/ADT/Twine.h" #include "llvm/CodeGen/AsmPrinter.h" -#include "llvm/CodeGen/MachineConstantPool.h" -#include "llvm/CodeGen/MachineFunctionPass.h" +#include "llvm/CodeGen/MachineBasicBlock.h" +#include "llvm/CodeGen/MachineFunction.h" #include "llvm/CodeGen/MachineInstr.h" -#include "llvm/CodeGen/MachineInstrBuilder.h" #include "llvm/CodeGen/MachineModuleInfoImpls.h" +#include "llvm/CodeGen/MachineOperand.h" #include "llvm/CodeGen/MachineRegisterInfo.h" #include "llvm/CodeGen/StackMaps.h" #include "llvm/CodeGen/TargetLoweringObjectFileImpl.h" -#include "llvm/IR/Constants.h" -#include "llvm/IR/DebugInfo.h" -#include "llvm/IR/DerivedTypes.h" -#include "llvm/IR/Mangler.h" +#include "llvm/IR/DataLayout.h" +#include "llvm/IR/GlobalValue.h" #include "llvm/IR/Module.h" #include "llvm/MC/MCAsmInfo.h" #include "llvm/MC/MCContext.h" @@ -48,21 +49,30 @@ #include "llvm/MC/MCSectionELF.h" #include "llvm/MC/MCSectionMachO.h" #include "llvm/MC/MCStreamer.h" +#include "llvm/MC/MCSymbol.h" #include "llvm/MC/MCSymbolELF.h" +#include "llvm/MC/SectionKind.h" +#include "llvm/Support/Casting.h" +#include "llvm/Support/CodeGen.h" #include "llvm/Support/Debug.h" #include "llvm/Support/ELF.h" #include "llvm/Support/ErrorHandling.h" -#include "llvm/Support/MathExtras.h" -#include "llvm/Support/TargetRegistry.h" +#include "llvm/Support/MachO.h" #include "llvm/Support/raw_ostream.h" -#include "llvm/Target/TargetInstrInfo.h" -#include "llvm/Target/TargetOptions.h" -#include "llvm/Target/TargetRegisterInfo.h" +#include "llvm/Support/TargetRegistry.h" +#include "llvm/Target/TargetMachine.h" +#include <algorithm> +#include <cassert> +#include <cstdint> +#include <memory> +#include <new> + using namespace llvm; #define DEBUG_TYPE "asmprinter" namespace { + class PPCAsmPrinter : public AsmPrinter { protected: MapVector<MCSymbol *, MCSymbol *> TOC; @@ -78,11 +88,11 @@ public: MCSymbol *lookUpOrCreateTOCEntry(MCSymbol *Sym); - virtual bool doInitialization(Module &M) override { + bool doInitialization(Module &M) override { if (!TOC.empty()) TOC.clear(); return AsmPrinter::doInitialization(M); - } + } void EmitInstruction(const MachineInstr *MI) override; @@ -141,7 +151,8 @@ public: bool doFinalization(Module &M) override; void EmitStartOfAsmFile(Module &M) override; }; -} // end of anonymous namespace + +} // end anonymous namespace /// stripRegisterPrefix - This method strips the character prefix from a /// register name so that only the number is left. Used by for linux asm. diff --git a/llvm/lib/Target/PowerPC/PPCBoolRetToInt.cpp b/llvm/lib/Target/PowerPC/PPCBoolRetToInt.cpp index b0c7bedb59c..93c201d0386 100644 --- a/llvm/lib/Target/PowerPC/PPCBoolRetToInt.cpp +++ b/llvm/lib/Target/PowerPC/PPCBoolRetToInt.cpp @@ -1,4 +1,4 @@ -//===- PPCBoolRetToInt.cpp - Convert bool literals to i32 if they are returned ==// +//===- PPCBoolRetToInt.cpp ------------------------------------------------===// // // The LLVM Compiler Infrastructure // @@ -33,15 +33,26 @@ //===----------------------------------------------------------------------===// #include "PPC.h" -#include "llvm/Transforms/Scalar.h" +#include "llvm/ADT/DenseMap.h" #include "llvm/ADT/SmallPtrSet.h" +#include "llvm/ADT/SmallVector.h" #include "llvm/ADT/Statistic.h" +#include "llvm/ADT/STLExtras.h" +#include "llvm/IR/Argument.h" #include "llvm/IR/Constants.h" #include "llvm/IR/Dominators.h" +#include "llvm/IR/Function.h" +#include "llvm/IR/Instruction.h" #include "llvm/IR/Instructions.h" #include "llvm/IR/IntrinsicInst.h" -#include "llvm/Support/raw_ostream.h" +#include "llvm/IR/OperandTraits.h" +#include "llvm/IR/Type.h" +#include "llvm/IR/Use.h" +#include "llvm/IR/User.h" +#include "llvm/IR/Value.h" +#include "llvm/Support/Casting.h" #include "llvm/Pass.h" +#include <cassert> using namespace llvm; @@ -57,7 +68,6 @@ STATISTIC(NumBoolToIntPromotion, "Total number of times a bool was promoted to an int"); class PPCBoolRetToInt : public FunctionPass { - static SmallPtrSet<Value *, 8> findAllDefs(Value *V) { SmallPtrSet<Value *, 8> Defs; SmallVector<Value *, 8> WorkList; @@ -66,7 +76,7 @@ class PPCBoolRetToInt : public FunctionPass { while (!WorkList.empty()) { Value *Curr = WorkList.back(); WorkList.pop_back(); - User *CurrUser = dyn_cast<User>(Curr); + auto *CurrUser = dyn_cast<User>(Curr); // Operands of CallInst are skipped because they may not be Bool type, // and their positions are defined by ABI. if (CurrUser && !isa<CallInst>(Curr)) @@ -80,9 +90,9 @@ class PPCBoolRetToInt : public FunctionPass { // Translate a i1 value to an equivalent i32 value: static Value *translate(Value *V) { Type *Int32Ty = Type::getInt32Ty(V->getContext()); - if (Constant *C = dyn_cast<Constant>(V)) + if (auto *C = dyn_cast<Constant>(V)) return ConstantExpr::getZExt(C, Int32Ty); - if (PHINode *P = dyn_cast<PHINode>(V)) { + if (auto *P = dyn_cast<PHINode>(V)) { // Temporarily set the operands to 0. We'll fix this later in // runOnUse. Value *Zero = Constant::getNullValue(Int32Ty); @@ -93,8 +103,8 @@ class PPCBoolRetToInt : public FunctionPass { return Q; } - Argument *A = dyn_cast<Argument>(V); - Instruction *I = dyn_cast<Instruction>(V); + auto *A = dyn_cast<Argument>(V); + auto *I = dyn_cast<Instruction>(V); assert((A || I) && "Unknown value type"); auto InstPt = @@ -117,7 +127,7 @@ class PPCBoolRetToInt : public FunctionPass { // Condition 1 for (auto &BB : F) for (auto &I : BB) - if (const PHINode *P = dyn_cast<PHINode>(&I)) + if (const auto *P = dyn_cast<PHINode>(&I)) if (P->getType()->isIntegerTy(1)) Promotable.insert(P); @@ -134,13 +144,14 @@ class PPCBoolRetToInt : public FunctionPass { }; const auto &Users = P->users(); const auto &Operands = P->operands(); - if (!all_of(Users, IsValidUser) || !all_of(Operands, IsValidOperand)) + if (!llvm::all_of(Users, IsValidUser) || + !llvm::all_of(Operands, IsValidOperand)) ToRemove.push_back(P); } // Iterate to convergence auto IsPromotable = [&Promotable] (const Value *V) -> bool { - const PHINode *Phi = dyn_cast<PHINode>(V); + const auto *Phi = dyn_cast<PHINode>(V); return !Phi || Promotable.count(Phi); }; while (!ToRemove.empty()) { @@ -152,7 +163,8 @@ class PPCBoolRetToInt : public FunctionPass { // Condition 4 and 5 const auto &Users = P->users(); const auto &Operands = P->operands(); - if (!all_of(Users, IsPromotable) || !all_of(Operands, IsPromotable)) + if (!llvm::all_of(Users, IsPromotable) || + !llvm::all_of(Operands, IsPromotable)) ToRemove.push_back(P); } } @@ -164,11 +176,12 @@ class PPCBoolRetToInt : public FunctionPass { public: static char ID; + PPCBoolRetToInt() : FunctionPass(ID) { initializePPCBoolRetToIntPass(*PassRegistry::getPassRegistry()); } - bool runOnFunction(Function &F) { + bool runOnFunction(Function &F) override { if (skipFunction(F)) return false; @@ -177,12 +190,12 @@ class PPCBoolRetToInt : public FunctionPass { bool Changed = false; for (auto &BB : F) { for (auto &I : BB) { - if (ReturnInst *R = dyn_cast<ReturnInst>(&I)) + if (auto *R = dyn_cast<ReturnInst>(&I)) if (F.getReturnType()->isIntegerTy(1)) Changed |= runOnUse(R->getOperandUse(0), PromotablePHINodes, Bool2IntMap); - if (CallInst *CI = dyn_cast<CallInst>(&I)) + if (auto *CI = dyn_cast<CallInst>(&I)) for (auto &U : CI->operands()) if (U->getType()->isIntegerTy(1)) Changed |= runOnUse(U, PromotablePHINodes, Bool2IntMap); @@ -197,7 +210,7 @@ class PPCBoolRetToInt : public FunctionPass { auto Defs = findAllDefs(U); // If the values are all Constants or Arguments, don't bother - if (none_of(Defs, isa<Instruction, Value *>)) + if (llvm::none_of(Defs, isa<Instruction, Value *>)) return false; // Presently, we only know how to handle PHINode, Constant, Arguments and @@ -209,7 +222,7 @@ class PPCBoolRetToInt : public FunctionPass { return false; for (Value *V : Defs) - if (const PHINode *P = dyn_cast<PHINode>(V)) + if (const auto *P = dyn_cast<PHINode>(V)) if (!PromotablePHINodes.count(P)) return false; @@ -226,8 +239,8 @@ class PPCBoolRetToInt : public FunctionPass { // Replace the operands of the translated instructions. They were set to // zero in the translate function. for (auto &Pair : BoolToIntMap) { - User *First = dyn_cast<User>(Pair.first); - User *Second = dyn_cast<User>(Pair.second); + auto *First = dyn_cast<User>(Pair.first); + auto *Second = dyn_cast<User>(Pair.second); assert((!First || Second) && "translated from user to non-user!?"); // Operands of CallInst are skipped because they may not be Bool type, // and their positions are defined by ABI. @@ -238,19 +251,20 @@ class PPCBoolRetToInt : public FunctionPass { Value *IntRetVal = BoolToIntMap[U]; Type *Int1Ty = Type::getInt1Ty(U->getContext()); - Instruction *I = cast<Instruction>(U.getUser()); + auto *I = cast<Instruction>(U.getUser()); Value *BackToBool = new TruncInst(IntRetVal, Int1Ty, "backToBool", I); U.set(BackToBool); return true; } - void getAnalysisUsage(AnalysisUsage &AU) const { + void getAnalysisUsage(AnalysisUsage &AU) const override { AU.addPreserved<DominatorTreeWrapperPass>(); FunctionPass::getAnalysisUsage(AU); } }; -} + +} // end anonymous namespace char PPCBoolRetToInt::ID = 0; INITIALIZE_PASS(PPCBoolRetToInt, "bool-ret-to-int", diff --git a/llvm/utils/TableGen/InstrInfoEmitter.cpp b/llvm/utils/TableGen/InstrInfoEmitter.cpp index a7abf61ac28..ab7d964cd67 100644 --- a/llvm/utils/TableGen/InstrInfoEmitter.cpp +++ b/llvm/utils/TableGen/InstrInfoEmitter.cpp @@ -13,22 +13,29 @@ //===----------------------------------------------------------------------===// #include "CodeGenDAGPatterns.h" +#include "CodeGenInstruction.h" #include "CodeGenSchedule.h" #include "CodeGenTarget.h" #include "SequenceToOffsetTable.h" #include "TableGenBackends.h" +#include "llvm/ADT/ArrayRef.h" #include "llvm/ADT/StringExtras.h" +#include "llvm/Support/Casting.h" +#include "llvm/Support/raw_ostream.h" #include "llvm/TableGen/Error.h" #include "llvm/TableGen/Record.h" #include "llvm/TableGen/TableGenBackend.h" -#include <algorithm> -#include <cstdio> +#include <cassert> +#include <cstdint> #include <map> +#include <string> +#include <utility> #include <vector> using namespace llvm; namespace { + class InstrInfoEmitter { RecordKeeper &Records; CodeGenDAGPatterns CDP; @@ -50,7 +57,7 @@ private: /// and instruction operand indices as their values. The values of this map /// are lists of instruction names. typedef std::map<std::map<unsigned, unsigned>, - std::vector<std::string> > OpNameMapTy; + std::vector<std::string>> OpNameMapTy; typedef std::map<std::string, unsigned>::iterator StrUintMapIter; void emitRecord(const CodeGenInstruction &Inst, unsigned Num, Record *InstrInfo, @@ -70,6 +77,7 @@ private: void EmitOperandInfo(raw_ostream &OS, OperandInfoMapTy &OperandInfoIDs); std::vector<std::string> GetOperandInfo(const CodeGenInstruction &Inst); }; + } // end anonymous namespace static void PrintDefList(const std::vector<Record*> &Uses, @@ -106,7 +114,7 @@ InstrInfoEmitter::GetOperandInfo(const CodeGenInstruction &Inst) { for (unsigned j = 0, e = Op.MINumOperands; j != e; ++j) { OperandList.push_back(Op); - Record *OpR = cast<DefInit>(MIOI->getArg(j))->getDef(); + auto *OpR = cast<DefInit>(MIOI->getArg(j))->getDef(); OperandList.back().Rec = OpR; } } @@ -202,7 +210,6 @@ void InstrInfoEmitter::initOperandMapData( const std::string &Namespace, std::map<std::string, unsigned> &Operands, OpNameMapTy &OperandMap) { - unsigned NumOperands = 0; for (const CodeGenInstruction *Inst : NumberedInstructions) { if (!Inst->TheDef->getValueAsBit("UseNamedOperandTable")) @@ -236,7 +243,6 @@ void InstrInfoEmitter::initOperandMapData( void InstrInfoEmitter::emitOperandNameMappings(raw_ostream &OS, const CodeGenTarget &Target, ArrayRef<const CodeGenInstruction*> NumberedInstructions) { - const std::string &Namespace = Target.getInstNamespace(); std::string OpNameNS = "OpName"; // Map of operand names to their enumeration value. This will be used to @@ -301,7 +307,6 @@ void InstrInfoEmitter::emitOperandNameMappings(raw_ostream &OS, OS << "} // end namespace " << Namespace << "\n"; OS << "} // end namespace llvm\n"; OS << "#endif //GET_INSTRINFO_NAMED_OPS\n\n"; - } /// Generate an enum for all the operand types for this target, under the @@ -430,7 +435,7 @@ void InstrInfoEmitter::run(raw_ostream &OS) { OS << "struct " << ClassName << " : public TargetInstrInfo {\n" << " explicit " << ClassName << "(int CFSetupOpcode = -1, int CFDestroyOpcode = -1, int CatchRetOpcode = -1, int ReturnOpcode = -1);\n" - << " ~" << ClassName << "() override {}\n" + << " ~" << ClassName << "() override = default;\n" << "};\n"; OS << "} // end llvm namespace\n"; @@ -516,7 +521,7 @@ void InstrInfoEmitter::emitRecord(const CodeGenInstruction &Inst, unsigned Num, PrintFatalError("no TSFlags?"); uint64_t Value = 0; for (unsigned i = 0, e = TSF->getNumBits(); i != e; ++i) { - if (BitInit *Bit = dyn_cast<BitInit>(TSF->getBit(i))) + if (const auto *Bit = dyn_cast<BitInit>(TSF->getBit(i))) Value |= uint64_t(Bit->getValue()) << i; else PrintFatalError("Invalid TSFlags bit in " + Inst.TheDef->getName()); @@ -563,7 +568,6 @@ void InstrInfoEmitter::emitRecord(const CodeGenInstruction &Inst, unsigned Num, // emitEnums - Print out enum values for all of the instructions. void InstrInfoEmitter::emitEnums(raw_ostream &OS) { - OS << "#ifdef GET_INSTRINFO_ENUM\n"; OS << "#undef GET_INSTRINFO_ENUM\n"; |
