diff options
| -rw-r--r-- | llvm/lib/Target/ARM/AsmParser/ARMAsmParser.cpp | 14 | ||||
| -rw-r--r-- | llvm/test/MC/ARM/thumb2-narrow-dp.ll | 2 | ||||
| -rw-r--r-- | llvm/test/MC/ARM/thumb_rewrites.s | 1 |
3 files changed, 14 insertions, 3 deletions
diff --git a/llvm/lib/Target/ARM/AsmParser/ARMAsmParser.cpp b/llvm/lib/Target/ARM/AsmParser/ARMAsmParser.cpp index ede7549e187..e928989e5e3 100644 --- a/llvm/lib/Target/ARM/AsmParser/ARMAsmParser.cpp +++ b/llvm/lib/Target/ARM/AsmParser/ARMAsmParser.cpp @@ -8215,8 +8215,16 @@ bool ARMAsmParser::processInstruction(MCInst &Inst, // If the destination and first source operand are the same, and // there's no setting of the flags, use encoding T2 instead of T3. // Note that this is only for ADD, not SUB. This mirrors the system - // 'as' behaviour. Make sure the wide encoding wasn't explicit. - if (Inst.getOperand(0).getReg() != Inst.getOperand(1).getReg() || + // 'as' behaviour. Also take advantage of ADD being commutative. + // Make sure the wide encoding wasn't explicit. + bool Swap = false; + auto DestReg = Inst.getOperand(0).getReg(); + bool Transform = DestReg == Inst.getOperand(1).getReg(); + if (!Transform && DestReg == Inst.getOperand(2).getReg()) { + Transform = true; + Swap = true; + } + if (!Transform || Inst.getOperand(5).getReg() != 0 || (static_cast<ARMOperand &>(*Operands[3]).isToken() && static_cast<ARMOperand &>(*Operands[3]).getToken() == ".w")) @@ -8225,7 +8233,7 @@ bool ARMAsmParser::processInstruction(MCInst &Inst, TmpInst.setOpcode(ARM::tADDhirr); TmpInst.addOperand(Inst.getOperand(0)); TmpInst.addOperand(Inst.getOperand(0)); - TmpInst.addOperand(Inst.getOperand(2)); + TmpInst.addOperand(Inst.getOperand(Swap ? 1 : 2)); TmpInst.addOperand(Inst.getOperand(3)); TmpInst.addOperand(Inst.getOperand(4)); Inst = TmpInst; diff --git a/llvm/test/MC/ARM/thumb2-narrow-dp.ll b/llvm/test/MC/ARM/thumb2-narrow-dp.ll index 0c2aae91643..050e9713399 100644 --- a/llvm/test/MC/ARM/thumb2-narrow-dp.ll +++ b/llvm/test/MC/ARM/thumb2-narrow-dp.ll @@ -44,6 +44,8 @@ // CHECK: adds r0, r2, r1 @ encoding: [0x50,0x18] ADDS r2, r2, r1 // ADDS has T1 narrow 3 operand // CHECK: adds r2, r2, r1 @ encoding: [0x52,0x18] + ADD r3, r1, r3 // T2 +// CHECK: add r3, r1 @ encoding: [0x0b,0x44] IT EQ // CHECK: it eq @ encoding: [0x08,0xbf] diff --git a/llvm/test/MC/ARM/thumb_rewrites.s b/llvm/test/MC/ARM/thumb_rewrites.s index e9f03d6b9a5..06c77e89862 100644 --- a/llvm/test/MC/ARM/thumb_rewrites.s +++ b/llvm/test/MC/ARM/thumb_rewrites.s @@ -1,4 +1,5 @@ @ RUN: llvm-mc -triple thumbv6m -show-encoding < %s | FileCheck %s +@ RUN: llvm-mc -triple thumbv7m -show-encoding < %s | FileCheck %s adds r1, r1, #3 @ CHECK: adds r1, r1, #3 @ encoding: [0xc9,0x1c] |
