diff options
| -rw-r--r-- | llvm/test/CodeGen/ARM/GlobalISel/arm-legalizer.mir | 292 |
1 files changed, 162 insertions, 130 deletions
diff --git a/llvm/test/CodeGen/ARM/GlobalISel/arm-legalizer.mir b/llvm/test/CodeGen/ARM/GlobalISel/arm-legalizer.mir index 6ac44aaad72..816c042a6d5 100644 --- a/llvm/test/CodeGen/ARM/GlobalISel/arm-legalizer.mir +++ b/llvm/test/CodeGen/ARM/GlobalISel/arm-legalizer.mir @@ -32,8 +32,7 @@ define void @test_shl_s32() { ret void } define void @test_load_from_stack() { ret void } - define void @test_legal_loads() #0 { ret void } - define void @test_legal_stores() #0 { ret void } + define void @test_legal_loads_stores() #0 { ret void } define void @test_gep() { ret void } @@ -64,15 +63,17 @@ tracksRegLiveness: true registers: - { id: 0, class: _ } - { id: 1, class: _ } + - { id: 2, class: _ } body: | bb.0: liveins: %r0 - %0(s8) = G_CONSTANT i8 42 - %1(s32) = G_SEXT %0 + %0(p0) = COPY %r0 + %1(s8) = G_LOAD %0(p0) :: (load 1) + %2(s32) = G_SEXT %1 ; G_SEXT with s8 is legal, so we should find it unchanged in the output ; CHECK: {{%[0-9]+}}:_(s32) = G_SEXT {{%[0-9]+}} - %r0 = COPY %1(s32) + %r0 = COPY %2(s32) BX_RET 14, _, implicit %r0 ... --- @@ -86,15 +87,17 @@ tracksRegLiveness: true registers: - { id: 0, class: _ } - { id: 1, class: _ } + - { id: 2, class: _ } body: | bb.0: liveins: %r0 - %0(s16) = G_CONSTANT i16 42 - %1(s32) = G_ZEXT %0 + %0(p0) = COPY %r0 + %1(s16) = G_LOAD %0 :: (load 2) + %2(s32) = G_ZEXT %1 ; G_ZEXT with s16 is legal, so we should find it unchanged in the output ; CHECK: {{%[0-9]+}}:_(s32) = G_ZEXT {{%[0-9]+}} - %r0 = COPY %1(s32) + %r0 = COPY %2(s32) BX_RET 14, _, implicit %r0 ... --- @@ -110,19 +113,23 @@ registers: - { id: 1, class: _ } - { id: 2, class: _ } - { id: 3, class: _ } + - { id: 4, class: _ } + - { id: 5, class: _ } body: | bb.0: liveins: %r0, %r1 - %0(s8) = G_CONSTANT i8 12 - %1(s8) = G_CONSTANT i8 30 - %2(s8) = G_ADD %0, %1 + %0(p0) = COPY %r0 + %1(s8) = G_LOAD %0 :: (load 1) + %2(p0) = COPY %r0 + %3(s8) = G_LOAD %2 :: (load 1) + %4(s8) = G_ADD %1, %3 ; G_ADD with s8 should widen ; CHECK-NOT: {{%[0-9]+}}:_(s8) = G_ADD {{%[0-9]+, %[0-9]+}} ; CHECK: {{%[0-9]+}}:_(s32) = G_ADD {{%[0-9]+, %[0-9]+}} ; CHECK-NOT: {{%[0-9]+}}:_(s8) = G_ADD {{%[0-9]+, %[0-9]+}} - %3(s32) = G_SEXT %2(s8) - %r0 = COPY %3(s32) + %5(s32) = G_SEXT %4(s8) + %r0 = COPY %5(s32) BX_RET 14, _, implicit %r0 ... --- @@ -138,21 +145,24 @@ registers: - { id: 1, class: _ } - { id: 2, class: _ } - { id: 3, class: _ } + - { id: 4, class: _ } + - { id: 5, class: _ } body: | bb.0: liveins: %r0, %r1 - %0(s16) = G_CONSTANT i16 32 - %1(s16) = G_CONSTANT i16 10 - %2(s16) = G_ADD %0, %1 + %0(p0) = COPY %r0 + %1(s16) = G_LOAD %0 :: (load 2) + %2(p0) = COPY %r0 + %3(s16) = G_LOAD %2 :: (load 2) + %4(s16) = G_ADD %1, %3 ; G_ADD with s16 should widen ; CHECK-NOT: {{%[0-9]+}}:_(s16) = G_ADD {{%[0-9]+, %[0-9]+}} ; CHECK: {{%[0-9]+}}:_(s32) = G_ADD {{%[0-9]+, %[0-9]+}} ; CHECK-NOT: {{%[0-9]+}}:_(s16) = G_ADD {{%[0-9]+, %[0-9]+}} - %3(s32) = G_SEXT %2(s16) - %r0 = COPY %3(s32) + %5(s32) = G_SEXT %4(s16) + %r0 = COPY %5(s32) BX_RET 14, _, implicit %r0 - ... --- name: test_add_s32 @@ -192,19 +202,23 @@ registers: - { id: 1, class: _ } - { id: 2, class: _ } - { id: 3, class: _ } + - { id: 4, class: _ } + - { id: 5, class: _ } body: | bb.0: liveins: %r0, %r1 - %0(s8) = G_CONSTANT i8 48 - %1(s8) = G_CONSTANT i8 6 - %2(s8) = G_SUB %0, %1 + %0(p0) = COPY %r0 + %1(s8) = G_LOAD %0 :: (load 1) + %2(p0) = COPY %r0 + %3(s8) = G_LOAD %2 :: (load 1) + %4(s8) = G_SUB %1, %3 ; G_SUB with s8 should widen ; CHECK-NOT: {{%[0-9]+}}:_(s8) = G_SUB {{%[0-9]+, %[0-9]+}} ; CHECK: {{%[0-9]+}}:_(s32) = G_SUB {{%[0-9]+, %[0-9]+}} ; CHECK-NOT: {{%[0-9]+}}:_(s8) = G_SUB {{%[0-9]+, %[0-9]+}} - %3(s32) = G_SEXT %2(s8) - %r0 = COPY %3(s32) + %5(s32) = G_SEXT %4(s8) + %r0 = COPY %5(s32) BX_RET 14, _, implicit %r0 ... --- @@ -220,21 +234,24 @@ registers: - { id: 1, class: _ } - { id: 2, class: _ } - { id: 3, class: _ } + - { id: 4, class: _ } + - { id: 5, class: _ } body: | bb.0: liveins: %r0, %r1 - %0(s16) = G_CONSTANT i16 58 - %1(s16) = G_CONSTANT i16 16 - %2(s16) = G_SUB %0, %1 + %0(p0) = COPY %r0 + %1(s16) = G_LOAD %0 :: (load 2) + %2(p0) = COPY %r0 + %3(s16) = G_LOAD %2 :: (load 2) + %4(s16) = G_SUB %1, %3 ; G_SUB with s16 should widen ; CHECK-NOT: {{%[0-9]+}}:_(s16) = G_SUB {{%[0-9]+, %[0-9]+}} ; CHECK: {{%[0-9]+}}:_(s32) = G_SUB {{%[0-9]+, %[0-9]+}} ; CHECK-NOT: {{%[0-9]+}}:_(s16) = G_SUB {{%[0-9]+, %[0-9]+}} - %3(s32) = G_SEXT %2(s16) - %r0 = COPY %3(s32) + %5(s32) = G_SEXT %4(s16) + %r0 = COPY %5(s32) BX_RET 14, _, implicit %r0 - ... --- name: test_sub_s32 @@ -274,19 +291,23 @@ registers: - { id: 1, class: _ } - { id: 2, class: _ } - { id: 3, class: _ } + - { id: 4, class: _ } + - { id: 5, class: _ } body: | bb.0: liveins: %r0, %r1 - %0(s8) = G_CONSTANT i8 7 - %1(s8) = G_CONSTANT i8 6 - %2(s8) = G_MUL %0, %1 + %0(p0) = COPY %r0 + %1(s8) = G_LOAD %0 :: (load 1) + %2(p0) = COPY %r0 + %3(s8) = G_LOAD %2 :: (load 1) + %4(s8) = G_MUL %1, %3 ; G_MUL with s8 should widen ; CHECK-NOT: {{%[0-9]+}}:_(s8) = G_MUL {{%[0-9]+, %[0-9]+}} ; CHECK: {{%[0-9]+}}:_(s32) = G_MUL {{%[0-9]+, %[0-9]+}} ; CHECK-NOT: {{%[0-9]+}}:_(s8) = G_MUL {{%[0-9]+, %[0-9]+}} - %3(s32) = G_SEXT %2(s8) - %r0 = COPY %3(s32) + %5(s32) = G_SEXT %4(s8) + %r0 = COPY %5(s32) BX_RET 14, _, implicit %r0 ... --- @@ -302,21 +323,24 @@ registers: - { id: 1, class: _ } - { id: 2, class: _ } - { id: 3, class: _ } + - { id: 4, class: _ } + - { id: 5, class: _ } body: | bb.0: liveins: %r0, %r1 - %0(s16) = G_CONSTANT i16 3 - %1(s16) = G_CONSTANT i16 14 - %2(s16) = G_MUL %0, %1 + %0(p0) = COPY %r0 + %1(s16) = G_LOAD %0 :: (load 2) + %2(p0) = COPY %r0 + %3(s16) = G_LOAD %2 :: (load 2) + %4(s16) = G_MUL %1, %3 ; G_MUL with s16 should widen ; CHECK-NOT: {{%[0-9]+}}:_(s16) = G_MUL {{%[0-9]+, %[0-9]+}} ; CHECK: {{%[0-9]+}}:_(s32) = G_MUL {{%[0-9]+, %[0-9]+}} ; CHECK-NOT: {{%[0-9]+}}:_(s16) = G_MUL {{%[0-9]+, %[0-9]+}} - %3(s32) = G_SEXT %2(s16) - %r0 = COPY %3(s32) + %5(s32) = G_SEXT %4(s16) + %r0 = COPY %5(s32) BX_RET 14, _, implicit %r0 - ... --- name: test_mul_s32 @@ -356,19 +380,23 @@ registers: - { id: 1, class: _ } - { id: 2, class: _ } - { id: 3, class: _ } + - { id: 4, class: _ } + - { id: 5, class: _ } body: | bb.0: liveins: %r0, %r1 - %0(s8) = G_CONSTANT i8 46 - %1(s8) = G_CONSTANT i8 58 - %2(s8) = G_AND %0, %1 + %0(p0) = COPY %r0 + %1(s8) = G_LOAD %0 :: (load 1) + %2(p0) = COPY %r0 + %3(s8) = G_LOAD %2 :: (load 1) + %4(s8) = G_AND %1, %3 ; G_AND with s8 should widen ; CHECK-NOT: {{%[0-9]+}}:_(s8) = G_AND {{%[0-9]+, %[0-9]+}} ; CHECK: {{%[0-9]+}}:_(s32) = G_AND {{%[0-9]+, %[0-9]+}} ; CHECK-NOT: {{%[0-9]+}}:_(s8) = G_AND {{%[0-9]+, %[0-9]+}} - %3(s32) = G_SEXT %2(s8) - %r0 = COPY %3(s32) + %5(s32) = G_SEXT %4(s8) + %r0 = COPY %5(s32) BX_RET 14, _, implicit %r0 ... --- @@ -384,21 +412,24 @@ registers: - { id: 1, class: _ } - { id: 2, class: _ } - { id: 3, class: _ } + - { id: 4, class: _ } + - { id: 5, class: _ } body: | bb.0: liveins: %r0, %r1 - %0(s16) = G_CONSTANT i16 43 - %1(s16) = G_CONSTANT i16 106 - %2(s16) = G_AND %0, %1 + %0(p0) = COPY %r0 + %1(s16) = G_LOAD %0 :: (load 2) + %2(p0) = COPY %r0 + %3(s16) = G_LOAD %2 :: (load 2) + %4(s16) = G_AND %1, %3 ; G_AND with s16 should widen ; CHECK-NOT: {{%[0-9]+}}:_(s16) = G_AND {{%[0-9]+, %[0-9]+}} ; CHECK: {{%[0-9]+}}:_(s32) = G_AND {{%[0-9]+, %[0-9]+}} ; CHECK-NOT: {{%[0-9]+}}:_(s16) = G_AND {{%[0-9]+, %[0-9]+}} - %3(s32) = G_SEXT %2(s16) - %r0 = COPY %3(s32) + %5(s32) = G_SEXT %4(s16) + %r0 = COPY %5(s32) BX_RET 14, _, implicit %r0 - ... --- name: test_and_s32 @@ -438,19 +469,23 @@ registers: - { id: 1, class: _ } - { id: 2, class: _ } - { id: 3, class: _ } + - { id: 4, class: _ } + - { id: 5, class: _ } body: | bb.0: liveins: %r0, %r1 - %0(s8) = G_CONSTANT i8 32 - %1(s8) = G_CONSTANT i8 10 - %2(s8) = G_OR %0, %1 + %0(p0) = COPY %r0 + %1(s8) = G_LOAD %0 :: (load 1) + %2(p0) = COPY %r0 + %3(s8) = G_LOAD %2 :: (load 1) + %4(s8) = G_OR %1, %3 ; G_OR with s8 should widen ; CHECK-NOT: {{%[0-9]+}}:_(s8) = G_OR {{%[0-9]+, %[0-9]+}} ; CHECK: {{%[0-9]+}}:_(s32) = G_OR {{%[0-9]+, %[0-9]+}} ; CHECK-NOT: {{%[0-9]+}}:_(s8) = G_OR {{%[0-9]+, %[0-9]+}} - %3(s32) = G_SEXT %2(s8) - %r0 = COPY %3(s32) + %5(s32) = G_SEXT %4(s8) + %r0 = COPY %5(s32) BX_RET 14, _, implicit %r0 ... --- @@ -466,21 +501,24 @@ registers: - { id: 1, class: _ } - { id: 2, class: _ } - { id: 3, class: _ } + - { id: 4, class: _ } + - { id: 5, class: _ } body: | bb.0: liveins: %r0, %r1 - %0(s16) = G_CONSTANT i16 34 - %1(s16) = G_CONSTANT i16 10 - %2(s16) = G_OR %0, %1 + %0(p0) = COPY %r0 + %1(s16) = G_LOAD %0 :: (load 2) + %2(p0) = COPY %r0 + %3(s16) = G_LOAD %2 :: (load 2) + %4(s16) = G_OR %1, %3 ; G_OR with s16 should widen ; CHECK-NOT: {{%[0-9]+}}:_(s16) = G_OR {{%[0-9]+, %[0-9]+}} ; CHECK: {{%[0-9]+}}:_(s32) = G_OR {{%[0-9]+, %[0-9]+}} ; CHECK-NOT: {{%[0-9]+}}:_(s16) = G_OR {{%[0-9]+, %[0-9]+}} - %3(s32) = G_SEXT %2(s16) - %r0 = COPY %3(s32) + %5(s32) = G_SEXT %4(s16) + %r0 = COPY %5(s32) BX_RET 14, _, implicit %r0 - ... --- name: test_or_s32 @@ -520,19 +558,23 @@ registers: - { id: 1, class: _ } - { id: 2, class: _ } - { id: 3, class: _ } + - { id: 4, class: _ } + - { id: 5, class: _ } body: | bb.0: liveins: %r0, %r1 - %0(s8) = G_CONSTANT i8 10 - %1(s8) = G_CONSTANT i8 32 - %2(s8) = G_XOR %0, %1 + %0(p0) = COPY %r0 + %1(s8) = G_LOAD %0 :: (load 1) + %2(p0) = COPY %r0 + %3(s8) = G_LOAD %2 :: (load 1) + %4(s8) = G_XOR %1, %3 ; G_XOR with s8 should widen ; CHECK-NOT: {{%[0-9]+}}:_(s8) = G_XOR {{%[0-9]+, %[0-9]+}} ; CHECK: {{%[0-9]+}}:_(s32) = G_XOR {{%[0-9]+, %[0-9]+}} ; CHECK-NOT: {{%[0-9]+}}:_(s8) = G_XOR {{%[0-9]+, %[0-9]+}} - %3(s32) = G_SEXT %2(s8) - %r0 = COPY %3(s32) + %5(s32) = G_SEXT %4(s8) + %r0 = COPY %5(s32) BX_RET 14, _, implicit %r0 ... --- @@ -548,21 +590,24 @@ registers: - { id: 1, class: _ } - { id: 2, class: _ } - { id: 3, class: _ } + - { id: 4, class: _ } + - { id: 5, class: _ } body: | bb.0: liveins: %r0, %r1 - %0(s16) = G_CONSTANT i16 40 - %1(s16) = G_CONSTANT i16 2 - %2(s16) = G_XOR %0, %1 + %0(p0) = COPY %r0 + %1(s16) = G_LOAD %0 :: (load 2) + %2(p0) = COPY %r0 + %3(s16) = G_LOAD %2 :: (load 2) + %4(s16) = G_XOR %1, %3 ; G_XOR with s16 should widen ; CHECK-NOT: {{%[0-9]+}}:_(s16) = G_XOR {{%[0-9]+, %[0-9]+}} ; CHECK: {{%[0-9]+}}:_(s32) = G_XOR {{%[0-9]+, %[0-9]+}} ; CHECK-NOT: {{%[0-9]+}}:_(s16) = G_XOR {{%[0-9]+, %[0-9]+}} - %3(s32) = G_SEXT %2(s16) - %r0 = COPY %3(s32) + %5(s32) = G_SEXT %4(s16) + %r0 = COPY %5(s32) BX_RET 14, _, implicit %r0 - ... --- name: test_xor_s32 @@ -691,47 +736,12 @@ body: | ; CHECK: {{%[0-9]+}}:_(s32) = G_LOAD [[FIVREG]](p0) :: (load 4) %0(p0) = G_FRAME_INDEX %fixed-stack.2 %1(s32) = G_LOAD %0(p0) :: (load 4) - BX_RET 14, _ -... ---- -name: test_legal_loads -# CHECK-LABEL: name: test_legal_loads -legalized: false -# CHECK: legalized: true -regBankSelected: false -selected: false -tracksRegLiveness: true -registers: - - { id: 0, class: _ } - - { id: 1, class: _ } - - { id: 2, class: _ } - - { id: 3, class: _ } - - { id: 4, class: _ } - - { id: 5, class: _ } - - { id: 6, class: _ } -body: | - bb.0: - liveins: %r0, %r1, %r2, %r3 - - ; These are all legal, so we should find them unchanged in the output - ; CHECK-DAG: {{%[0-9]+}}:_(s64) = G_LOAD %0 - ; CHECK-DAG: {{%[0-9]+}}:_(s32) = G_LOAD %0 - ; CHECK-DAG: {{%[0-9]+}}:_(s16) = G_LOAD %0 - ; CHECK-DAG: {{%[0-9]+}}:_(s8) = G_LOAD %0 - ; CHECK-DAG: {{%[0-9]+}}:_(s1) = G_LOAD %0 - ; CHECK-DAG: {{%[0-9]+}}:_(p0) = G_LOAD %0 - %0(p0) = COPY %r0 - %1(s32) = G_LOAD %0(p0) :: (load 4) - %2(s16) = G_LOAD %0(p0) :: (load 2) - %3(s8) = G_LOAD %0(p0) :: (load 1) - %4(s1) = G_LOAD %0(p0) :: (load 1) - %5(p0) = G_LOAD %0(p0) :: (load 4) - %6(s64) = G_LOAD %0(p0) :: (load 8) - BX_RET 14, _ + %r0 = COPY %1(s32) + BX_RET 14, _, implicit %r0 ... --- -name: test_legal_stores -# CHECK-LABEL: name: test_legal_stores +name: test_legal_loads_stores +# CHECK-LABEL: name: test_legal_loads_stores legalized: false # CHECK: legalized: true regBankSelected: false @@ -747,7 +757,7 @@ registers: - { id: 6, class: _ } body: | bb.0: - liveins: %r0, %r1, %r2, %r3, %r4, %r5, %r6, %d1 + liveins: %r0 ; These are all legal, so we should find them unchanged in the output ; CHECK-DAG: G_STORE {{%[0-9]+}}(s64), %0(p0) @@ -756,18 +766,24 @@ body: | ; CHECK-DAG: G_STORE {{%[0-9]+}}(s8), %0(p0) ; CHECK-DAG: G_STORE {{%[0-9]+}}(s1), %0(p0) ; CHECK-DAG: G_STORE {{%[0-9]+}}(p0), %0(p0) + ; CHECK-DAG: {{%[0-9]+}}:_(s64) = G_LOAD %0(p0) + ; CHECK-DAG: {{%[0-9]+}}:_(s32) = G_LOAD %0(p0) + ; CHECK-DAG: {{%[0-9]+}}:_(s16) = G_LOAD %0(p0) + ; CHECK-DAG: {{%[0-9]+}}:_(s8) = G_LOAD %0(p0) + ; CHECK-DAG: {{%[0-9]+}}:_(s1) = G_LOAD %0(p0) + ; CHECK-DAG: {{%[0-9]+}}:_(p0) = G_LOAD %0(p0) %0(p0) = COPY %r0 - %1(s64) = COPY %d1 + %1(s64) = G_LOAD %0(p0) :: (load 8) G_STORE %1(s64), %0(p0) :: (store 8) - %2(s32) = COPY %r2 + %2(s32) = G_LOAD %0(p0) :: (load 4) G_STORE %2(s32), %0(p0) :: (store 4) - %3(s16) = G_CONSTANT i16 42 + %3(s16) = G_LOAD %0(p0) :: (load 2) G_STORE %3(s16), %0(p0) :: (store 2) - %4(s8) = G_CONSTANT i8 21 + %4(s8) = G_LOAD %0(p0) :: (load 1) G_STORE %4(s8), %0(p0) :: (store 1) - %5(s1) = G_CONSTANT i1 1 + %5(s1) = G_LOAD %0(p0) :: (load 1) G_STORE %5(s1), %0(p0) :: (store 1) - %6(p0) = COPY %r6 + %6(p0) = G_LOAD %0(p0) :: (load 4) G_STORE %6(p0), %0(p0) :: (store 4) BX_RET 14, _ ... @@ -809,24 +825,32 @@ registers: - { id: 1, class: _ } - { id: 2, class: _ } - { id: 3, class: _ } + - { id: 4, class: _ } body: | bb.0: + liveins: %r0 + + %4(p0) = COPY %r0 + %0(s32) = G_CONSTANT 42 ; CHECK: {{%[0-9]+}}:_(s32) = G_CONSTANT 42 %1(s16) = G_CONSTANT i16 21 + G_STORE %1(s16), %4(p0) :: (store 2) ; CHECK-NOT: G_CONSTANT i16 ; CHECK: [[EXT:%[0-9]+]]:_(s32) = G_CONSTANT i32 21 ; CHECK: {{%[0-9]+}}:_(s16) = G_TRUNC [[EXT]](s32) ; CHECK-NOT: G_CONSTANT i16 %2(s8) = G_CONSTANT i8 10 + G_STORE %2(s8), %4(p0) :: (store 1) ; CHECK-NOT: G_CONSTANT i8 ; CHECK: [[EXT:%[0-9]+]]:_(s32) = G_CONSTANT i32 10 ; CHECK: {{%[0-9]+}}:_(s8) = G_TRUNC [[EXT]](s32) ; CHECK-NOT: G_CONSTANT i8 %3(s1) = G_CONSTANT i1 1 + G_STORE %3(s1), %4(p0) :: (store 1) ; CHECK-NOT: G_CONSTANT i1 ; CHECK: [[EXT:%[0-9]+]]:_(s32) = G_CONSTANT i32 -1 ; CHECK: {{%[0-9]+}}:_(s1) = G_TRUNC [[EXT]](s32) @@ -848,18 +872,22 @@ registers: - { id: 1, class: _ } - { id: 2, class: _ } - { id: 3, class: _ } + - { id: 4, class: _ } + - { id: 5, class: _ } body: | bb.0: liveins: %r0, %r1 - %0(s8) = G_CONSTANT i8 42 - %1(s8) = G_CONSTANT i8 43 - %2(s1) = G_ICMP intpred(ne), %0(s8), %1 + %0(p0) = COPY %r0 + %1(s8) = G_LOAD %0 :: (load 1) + %2(p0) = COPY %r1 + %3(s8) = G_LOAD %2 :: (load 1) + %4(s1) = G_ICMP intpred(ne), %1(s8), %3 ; G_ICMP with s8 should widen ; CHECK: {{%[0-9]+}}:_(s1) = G_ICMP intpred(ne), {{%[0-9]+}}(s32), {{%[0-9]+}} ; CHECK-NOT: {{%[0-9]+}}:_(s1) = G_ICMP intpred(ne), {{%[0-9]+}}(s8), {{%[0-9]+}} - %3(s32) = G_ZEXT %2(s1) - %r0 = COPY %3(s32) + %5(s32) = G_ZEXT %4(s1) + %r0 = COPY %5(s32) BX_RET 14, _, implicit %r0 ... --- @@ -875,18 +903,22 @@ registers: - { id: 1, class: _ } - { id: 2, class: _ } - { id: 3, class: _ } + - { id: 4, class: _ } + - { id: 5, class: _ } body: | bb.0: liveins: %r0, %r1 - %0(s16) = G_CONSTANT i16 42 - %1(s16) = G_CONSTANT i16 46 - %2(s1) = G_ICMP intpred(slt), %0(s16), %1 + %0(p0) = COPY %r0 + %1(s16) = G_LOAD %0 :: (load 2) + %2(p0) = COPY %r1 + %3(s16) = G_LOAD %2 :: (load 2) + %4(s1) = G_ICMP intpred(slt), %1(s16), %3 ; G_ICMP with s16 should widen ; CHECK: {{%[0-9]+}}:_(s1) = G_ICMP intpred(slt), {{%[0-9]+}}(s32), {{%[0-9]+}} ; CHECK-NOT: {{%[0-9]+}}:_(s1) = G_ICMP intpred(slt), {{%[0-9]+}}(s16), {{%[0-9]+}} - %3(s32) = G_ZEXT %2(s1) - %r0 = COPY %3(s32) + %5(s32) = G_ZEXT %4(s1) + %r0 = COPY %5(s32) BX_RET 14, _, implicit %r0 ... --- |
