diff options
| -rw-r--r-- | llvm/include/llvm/CodeGen/ValueTypes.h | 4 | ||||
| -rw-r--r-- | llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp | 4 | ||||
| -rw-r--r-- | llvm/lib/CodeGen/SelectionDAG/LegalizeTypesPromote.cpp | 2 | ||||
| -rw-r--r-- | llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp | 2 |
4 files changed, 8 insertions, 4 deletions
diff --git a/llvm/include/llvm/CodeGen/ValueTypes.h b/llvm/include/llvm/CodeGen/ValueTypes.h index 22538a73d0a..fe3ee6e7b66 100644 --- a/llvm/include/llvm/CodeGen/ValueTypes.h +++ b/llvm/include/llvm/CodeGen/ValueTypes.h @@ -261,6 +261,10 @@ namespace llvm { (isExtended() && isVector() && getSizeInBits()==128)); } + /// isByteSized - Return true if the bit size is a multiple of 8. + inline bool isByteSized() const { + return (getSizeInBits() & 7) == 0; + } /// bitsGT - Return true if this has more bits than VT. inline bool bitsGT(MVT VT) const { diff --git a/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp b/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp index ea96e5c9ce7..8696bcf63b9 100644 --- a/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp +++ b/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp @@ -1785,7 +1785,7 @@ SDOperand DAGCombiner::visitAND(SDNode *N) { // Loading a non-byte sized integer is only valid if the extra bits // in memory that complete the byte are zero, which is not known here. // TODO: remove isSimple check when apint codegen support lands. - EVT.isSimple() && EVT.getSizeInBits() == EVT.getStoreSizeInBits() && + EVT.isSimple() && EVT.isByteSized() && (!AfterLegalize || TLI.isLoadXLegal(ISD::ZEXTLOAD, EVT))) { MVT PtrType = N0.getOperand(1).getValueType(); // For big endian targets, we need to add an offset to the pointer to @@ -3181,7 +3181,7 @@ SDOperand DAGCombiner::ReduceLoadWidth(SDNode *N) { // Do not allow folding to a non-byte-sized integer here. These only // load correctly if the extra bits in memory that complete the byte // are zero, which is not known here. - VT.getSizeInBits() == VT.getStoreSizeInBits()) { + VT.isByteSized()) { assert(N0.getValueType().getSizeInBits() > EVTBits && "Cannot truncate to larger type!"); LoadSDNode *LN0 = cast<LoadSDNode>(N0); diff --git a/llvm/lib/CodeGen/SelectionDAG/LegalizeTypesPromote.cpp b/llvm/lib/CodeGen/SelectionDAG/LegalizeTypesPromote.cpp index b0a8475b33b..5c68fe2dc3d 100644 --- a/llvm/lib/CodeGen/SelectionDAG/LegalizeTypesPromote.cpp +++ b/llvm/lib/CodeGen/SelectionDAG/LegalizeTypesPromote.cpp @@ -94,7 +94,7 @@ SDOperand DAGTypeLegalizer::PromoteResult_Constant(SDNode *N) { MVT VT = N->getValueType(0); // Zero extend things like i1, sign extend everything else. It shouldn't // matter in theory which one we pick, but this tends to give better code? - unsigned Opc = VT != MVT::i1 ? ISD::SIGN_EXTEND : ISD::ZERO_EXTEND; + unsigned Opc = VT.isByteSized() ? ISD::SIGN_EXTEND : ISD::ZERO_EXTEND; SDOperand Result = DAG.getNode(Opc, TLI.getTypeToTransformTo(VT), SDOperand(N, 0)); assert(isa<ConstantSDNode>(Result) && "Didn't constant fold ext?"); diff --git a/llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp b/llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp index 81cdf4637fb..fe752de6445 100644 --- a/llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp +++ b/llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp @@ -250,7 +250,7 @@ void TargetLowering::computeRegisterProperties() { NumRegistersForVT[MVT::isVoid] = 0; // Find the largest integer register class. - unsigned LargestIntReg = MVT::i128; + unsigned LargestIntReg = MVT::LAST_INTEGER_VALUETYPE; for (; RegClassForVT[LargestIntReg] == 0; --LargestIntReg) assert(LargestIntReg != MVT::i1 && "No integer registers defined!"); |
