diff options
| -rw-r--r-- | llvm/lib/Target/AMDGPU/AMDGPU.h | 1 | ||||
| -rw-r--r-- | llvm/lib/Target/AMDGPU/AMDGPUInstrInfo.h | 1 | ||||
| -rw-r--r-- | llvm/lib/Target/AMDGPU/AMDGPURegisterInfo.h | 1 | ||||
| -rw-r--r-- | llvm/lib/Target/AMDGPU/AMDGPUSubtarget.cpp | 1 | ||||
| -rw-r--r-- | llvm/lib/Target/AMDGPU/Disassembler/AMDGPUDisassembler.cpp | 16 | ||||
| -rw-r--r-- | llvm/lib/Target/AMDGPU/MCTargetDesc/AMDGPUMCTargetDesc.h | 6 | ||||
| -rw-r--r-- | llvm/lib/Target/AMDGPU/SIMachineFunctionInfo.h | 1 | ||||
| -rw-r--r-- | llvm/lib/Target/AMDGPU/Utils/AMDGPUBaseInfo.cpp | 9 | ||||
| -rw-r--r-- | llvm/lib/Target/AMDGPU/Utils/AMDGPUBaseInfo.h | 4 | ||||
| -rw-r--r-- | llvm/lib/Target/AMDGPU/VOP2Instructions.td | 2 | ||||
| -rw-r--r-- | llvm/test/MC/Disassembler/AMDGPU/mac.txt | 19 |
11 files changed, 42 insertions, 19 deletions
diff --git a/llvm/lib/Target/AMDGPU/AMDGPU.h b/llvm/lib/Target/AMDGPU/AMDGPU.h index 6cca9ba016e..15c996b880e 100644 --- a/llvm/lib/Target/AMDGPU/AMDGPU.h +++ b/llvm/lib/Target/AMDGPU/AMDGPU.h @@ -11,6 +11,7 @@ #ifndef LLVM_LIB_TARGET_AMDGPU_AMDGPU_H #define LLVM_LIB_TARGET_AMDGPU_AMDGPU_H +#include "MCTargetDesc/AMDGPUMCTargetDesc.h" #include "llvm/Target/TargetMachine.h" namespace llvm { diff --git a/llvm/lib/Target/AMDGPU/AMDGPUInstrInfo.h b/llvm/lib/Target/AMDGPU/AMDGPUInstrInfo.h index a122fd612ec..12caa511834 100644 --- a/llvm/lib/Target/AMDGPU/AMDGPUInstrInfo.h +++ b/llvm/lib/Target/AMDGPU/AMDGPUInstrInfo.h @@ -21,7 +21,6 @@ #include "Utils/AMDGPUBaseInfo.h" #define GET_INSTRINFO_HEADER -#define GET_INSTRINFO_ENUM #include "AMDGPUGenInstrInfo.inc" namespace llvm { diff --git a/llvm/lib/Target/AMDGPU/AMDGPURegisterInfo.h b/llvm/lib/Target/AMDGPU/AMDGPURegisterInfo.h index ef51aad95dc..21e2d89fa7e 100644 --- a/llvm/lib/Target/AMDGPU/AMDGPURegisterInfo.h +++ b/llvm/lib/Target/AMDGPU/AMDGPURegisterInfo.h @@ -19,7 +19,6 @@ #include "llvm/Target/TargetRegisterInfo.h" #define GET_REGINFO_HEADER -#define GET_REGINFO_ENUM #include "AMDGPUGenRegisterInfo.inc" namespace llvm { diff --git a/llvm/lib/Target/AMDGPU/AMDGPUSubtarget.cpp b/llvm/lib/Target/AMDGPU/AMDGPUSubtarget.cpp index 92825684d90..695d51a5353 100644 --- a/llvm/lib/Target/AMDGPU/AMDGPUSubtarget.cpp +++ b/llvm/lib/Target/AMDGPU/AMDGPUSubtarget.cpp @@ -23,7 +23,6 @@ using namespace llvm; #define DEBUG_TYPE "amdgpu-subtarget" -#define GET_SUBTARGETINFO_ENUM #define GET_SUBTARGETINFO_TARGET_DESC #define GET_SUBTARGETINFO_CTOR #include "AMDGPUGenSubtargetInfo.inc" diff --git a/llvm/lib/Target/AMDGPU/Disassembler/AMDGPUDisassembler.cpp b/llvm/lib/Target/AMDGPU/Disassembler/AMDGPUDisassembler.cpp index d274d6a7505..4fb03b62bba 100644 --- a/llvm/lib/Target/AMDGPU/Disassembler/AMDGPUDisassembler.cpp +++ b/llvm/lib/Target/AMDGPU/Disassembler/AMDGPUDisassembler.cpp @@ -22,6 +22,7 @@ #include "AMDGPURegisterInfo.h" #include "SIDefines.h" #include "Utils/AMDGPUBaseInfo.h" +#include "MCTargetDesc/AMDGPUMCTargetDesc.h" #include "llvm/MC/MCContext.h" #include "llvm/MC/MCFixedLenDisassembler.h" @@ -105,10 +106,6 @@ static DecodeStatus decodeOperand_VSrcV216(MCInst &Inst, return addOperand(Inst, DAsm->decodeOperand_VSrcV216(Imm)); } -#define GET_SUBTARGETINFO_ENUM -#include "AMDGPUGenSubtargetInfo.inc" -#undef GET_SUBTARGETINFO_ENUM - #include "AMDGPUGenDisassemblerTables.inc" //===----------------------------------------------------------------------===// @@ -188,6 +185,17 @@ DecodeStatus AMDGPUDisassembler::getInstruction(MCInst &MI, uint64_t &Size, Res = tryDecodeInst(DecoderTableAMDGPU64, MI, QW, Address); } while (false); + if (Res && (MI.getOpcode() == AMDGPU::V_MAC_F32_e64_vi || + MI.getOpcode() == AMDGPU::V_MAC_F32_e64_si || + MI.getOpcode() == AMDGPU::V_MAC_F16_e64_vi)) { + // Insert dummy unused src2_modifiers. + int Src2ModIdx = AMDGPU::getNamedOperandIdx(MI.getOpcode(), + AMDGPU::OpName::src2_modifiers); + auto I = MI.begin(); + std::advance(I, Src2ModIdx); + MI.insert(I, MCOperand::createImm(0)); + } + Size = Res ? (MaxInstBytesNum - Bytes.size()) : 0; return Res; } diff --git a/llvm/lib/Target/AMDGPU/MCTargetDesc/AMDGPUMCTargetDesc.h b/llvm/lib/Target/AMDGPU/MCTargetDesc/AMDGPUMCTargetDesc.h index 548bad56e17..f80b5f3a6db 100644 --- a/llvm/lib/Target/AMDGPU/MCTargetDesc/AMDGPUMCTargetDesc.h +++ b/llvm/lib/Target/AMDGPU/MCTargetDesc/AMDGPUMCTargetDesc.h @@ -54,11 +54,17 @@ MCObjectWriter *createAMDGPUELFObjectWriter(bool Is64Bit, #define GET_REGINFO_ENUM #include "AMDGPUGenRegisterInfo.inc" +#undef GET_REGINFO_ENUM #define GET_INSTRINFO_ENUM +#define GET_INSTRINFO_OPERAND_ENUM #include "AMDGPUGenInstrInfo.inc" +#undef GET_INSTRINFO_OPERAND_ENUM +#undef GET_INSTRINFO_ENUM + #define GET_SUBTARGETINFO_ENUM #include "AMDGPUGenSubtargetInfo.inc" +#undef GET_SUBTARGETINFO_ENUM #endif diff --git a/llvm/lib/Target/AMDGPU/SIMachineFunctionInfo.h b/llvm/lib/Target/AMDGPU/SIMachineFunctionInfo.h index ec1d2c37115..ca492b98970 100644 --- a/llvm/lib/Target/AMDGPU/SIMachineFunctionInfo.h +++ b/llvm/lib/Target/AMDGPU/SIMachineFunctionInfo.h @@ -16,6 +16,7 @@ #include "AMDGPUMachineFunction.h" #include "SIRegisterInfo.h" +#include "MCTargetDesc/AMDGPUMCTargetDesc.h" #include "llvm/CodeGen/PseudoSourceValue.h" #include "llvm/MC/MCRegisterInfo.h" #include "llvm/Support/ErrorHandling.h" diff --git a/llvm/lib/Target/AMDGPU/Utils/AMDGPUBaseInfo.cpp b/llvm/lib/Target/AMDGPU/Utils/AMDGPUBaseInfo.cpp index 12778044bc9..abb489b88c5 100644 --- a/llvm/lib/Target/AMDGPU/Utils/AMDGPUBaseInfo.cpp +++ b/llvm/lib/Target/AMDGPU/Utils/AMDGPUBaseInfo.cpp @@ -36,19 +36,12 @@ #include <cstring> #include <utility> -#define GET_SUBTARGETINFO_ENUM -#include "AMDGPUGenSubtargetInfo.inc" -#undef GET_SUBTARGETINFO_ENUM +#include "MCTargetDesc/AMDGPUMCTargetDesc.h" -#define GET_REGINFO_ENUM -#include "AMDGPUGenRegisterInfo.inc" -#undef GET_REGINFO_ENUM #define GET_INSTRINFO_NAMED_OPS -#define GET_INSTRINFO_ENUM #include "AMDGPUGenInstrInfo.inc" #undef GET_INSTRINFO_NAMED_OPS -#undef GET_INSTRINFO_ENUM namespace { diff --git a/llvm/lib/Target/AMDGPU/Utils/AMDGPUBaseInfo.h b/llvm/lib/Target/AMDGPU/Utils/AMDGPUBaseInfo.h index 0ce90284d67..a8ce3c56551 100644 --- a/llvm/lib/Target/AMDGPU/Utils/AMDGPUBaseInfo.h +++ b/llvm/lib/Target/AMDGPU/Utils/AMDGPUBaseInfo.h @@ -21,10 +21,6 @@ #include <cstdint> #include <utility> -#define GET_INSTRINFO_OPERAND_ENUM -#include "AMDGPUGenInstrInfo.inc" -#undef GET_INSTRINFO_OPERAND_ENUM - namespace llvm { class FeatureBitset; diff --git a/llvm/lib/Target/AMDGPU/VOP2Instructions.td b/llvm/lib/Target/AMDGPU/VOP2Instructions.td index 562b56a3a68..2281f338ab4 100644 --- a/llvm/lib/Target/AMDGPU/VOP2Instructions.td +++ b/llvm/lib/Target/AMDGPU/VOP2Instructions.td @@ -181,6 +181,8 @@ class VOP_MADMK <ValueType vt> : VOPProfile <[vt, vt, vt, vt]> { def VOP_MADMK_F16 : VOP_MADMK <f16>; def VOP_MADMK_F32 : VOP_MADMK <f32>; +// FIXME: Remove src2_modifiers. It isn't used, so is wasting memory +// and processing time but it makes it easier to convert to mad. class VOP_MAC <ValueType vt> : VOPProfile <[vt, vt, vt, vt]> { let Ins32 = (ins Src0RC32:$src0, Src1RC32:$src1, VGPR_32:$src2); let Ins64 = getIns64<Src0RC64, Src1RC64, RegisterOperand<VGPR_32>, 3, diff --git a/llvm/test/MC/Disassembler/AMDGPU/mac.txt b/llvm/test/MC/Disassembler/AMDGPU/mac.txt new file mode 100644 index 00000000000..7f7f952655a --- /dev/null +++ b/llvm/test/MC/Disassembler/AMDGPU/mac.txt @@ -0,0 +1,19 @@ +# RUN: llvm-mc -arch=amdgcn -mcpu=tonga -disassemble -show-encoding < %s | FileCheck %s -check-prefix=VI + +# VI: v_mac_f32_e64 v0, v1, v2 mul:2 ; encoding: [0x00,0x00,0x16,0xd1,0x01,0x05,0x02,0x08] +0x00 0x00 0x16 0xd1 0x01 0x05 0x02 0x08 + +# VI: v_mac_f32_e64 v0, v1, v2 clamp ; encoding: [0x00,0x80,0x16,0xd1,0x01,0x05,0x02,0x00] +0x00 0x80 0x16 0xd1 0x01 0x05 0x02 0x00 + +# VI: v_mac_f32_e64 v0, v1, v2 clamp mul:2 ; encoding: [0x00,0x80,0x16,0xd1,0x01,0x05,0x02,0x08] +0x00 0x80 0x16 0xd1 0x01 0x05 0x02 0x08 + +# VI: v_mac_f16_e64 v0, v1, v2 mul:2 ; encoding: [0x00,0x00,0x23,0xd1,0x01,0x05,0x02,0x08] +0x00 0x00 0x23 0xd1 0x01 0x05 0x02 0x08 + +# VI: v_mac_f16_e64 v0, v1, v2 clamp ; encoding: [0x00,0x80,0x23,0xd1,0x01,0x05,0x02,0x00] +0x00 0x80 0x23 0xd1 0x01 0x05 0x02 0x00 + +# VI: v_mac_f16_e64 v0, v1, v2 clamp mul:2 ; encoding: [0x00,0x80,0x23,0xd1,0x01,0x05,0x02,0x08] +0x00 0x80 0x23 0xd1 0x01 0x05 0x02 0x08 |
