diff options
| -rw-r--r-- | llvm/lib/Target/AArch64/AsmParser/AArch64AsmParser.cpp | 14 | ||||
| -rw-r--r-- | llvm/lib/Target/AArch64/InstPrinter/AArch64InstPrinter.cpp | 15 | ||||
| -rw-r--r-- | llvm/lib/Target/AArch64/Utils/AArch64BaseInfo.h | 4 | ||||
| -rw-r--r-- | llvm/test/MC/AArch64/armv8.2a-at.s | 9 | ||||
| -rw-r--r-- | llvm/test/MC/Disassembler/AArch64/armv8.2a-at.txt | 9 |
5 files changed, 50 insertions, 1 deletions
diff --git a/llvm/lib/Target/AArch64/AsmParser/AArch64AsmParser.cpp b/llvm/lib/Target/AArch64/AsmParser/AArch64AsmParser.cpp index 48dfcbbf74a..e8bea2a68b2 100644 --- a/llvm/lib/Target/AArch64/AsmParser/AArch64AsmParser.cpp +++ b/llvm/lib/Target/AArch64/AsmParser/AArch64AsmParser.cpp @@ -2513,6 +2513,20 @@ bool AArch64AsmParser::parseSysAlias(StringRef Name, SMLoc NameLoc, } else if (!Op.compare_lower("s12e0w")) { // SYS #4, C7, C8, #7 SYS_ALIAS(4, 7, 8, 7); + } else if (!Op.compare_lower("s1e1rp")) { + if (getSTI().getFeatureBits()[AArch64::HasV8_2aOps]) { + // SYS #0, C7, C9, #0 + SYS_ALIAS(0, 7, 9, 0); + } else { + return TokError("AT S1E1RP requires ARMv8.2a"); + } + } else if (!Op.compare_lower("s1e1wp")) { + if (getSTI().getFeatureBits()[AArch64::HasV8_2aOps]) { + // SYS #0, C7, C9, #1 + SYS_ALIAS(0, 7, 9, 1); + } else { + return TokError("AT S1E1WP requires ARMv8.2a"); + } } else { return TokError("invalid operand for AT instruction"); } diff --git a/llvm/lib/Target/AArch64/InstPrinter/AArch64InstPrinter.cpp b/llvm/lib/Target/AArch64/InstPrinter/AArch64InstPrinter.cpp index 3153fb2d650..d8937b57e49 100644 --- a/llvm/lib/Target/AArch64/InstPrinter/AArch64InstPrinter.cpp +++ b/llvm/lib/Target/AArch64/InstPrinter/AArch64InstPrinter.cpp @@ -780,6 +780,21 @@ bool AArch64InstPrinter::printSysAlias(const MCInst *MI, break; } break; + case 9: + switch (Op1Val) { + default: + break; + case 0: + if (STI.getFeatureBits()[AArch64::HasV8_2aOps]) { + switch (Op2Val) { + default: + break; + case 0: Asm = "at\ts1e1rp"; break; + case 1: Asm = "at\ts1e1wp"; break; + } + } + break; + } } } else if (CnVal == 8) { // TLBI aliases diff --git a/llvm/lib/Target/AArch64/Utils/AArch64BaseInfo.h b/llvm/lib/Target/AArch64/Utils/AArch64BaseInfo.h index 79fb61502d8..5a6b54bbee8 100644 --- a/llvm/lib/Target/AArch64/Utils/AArch64BaseInfo.h +++ b/llvm/lib/Target/AArch64/Utils/AArch64BaseInfo.h @@ -337,7 +337,9 @@ namespace AArch64AT { S12E1R = 0x63c4, // 01 100 0111 1000 100 S12E1W = 0x63c5, // 01 100 0111 1000 101 S12E0R = 0x63c6, // 01 100 0111 1000 110 - S12E0W = 0x63c7 // 01 100 0111 1000 111 + S12E0W = 0x63c7, // 01 100 0111 1000 111 + S1E1RP = 0x43c8, // 01 000 0111 1001 000 + S1E1WP = 0x43c9 // 01 000 0111 1001 001 }; struct ATMapper : AArch64NamedImmMapper { diff --git a/llvm/test/MC/AArch64/armv8.2a-at.s b/llvm/test/MC/AArch64/armv8.2a-at.s new file mode 100644 index 00000000000..741f6922a9e --- /dev/null +++ b/llvm/test/MC/AArch64/armv8.2a-at.s @@ -0,0 +1,9 @@ +// RUN: llvm-mc -triple aarch64-none-linux-gnu -show-encoding -mattr=+v8.2a < %s | FileCheck %s +// RUN: not llvm-mc -triple aarch64-none-linux-gnu -show-encoding -mattr=-v8.2a < %s 2>&1 | FileCheck %s --check-prefix=ERROR + + at s1e1rp, x1 + at s1e1wp, x2 +// CHECK: at s1e1rp, x1 // encoding: [0x01,0x79,0x08,0xd5] +// CHECK: at s1e1wp, x2 // encoding: [0x22,0x79,0x08,0xd5] +// ERROR: error: AT S1E1RP requires ARMv8.2a +// ERROR: error: AT S1E1WP requires ARMv8.2a diff --git a/llvm/test/MC/Disassembler/AArch64/armv8.2a-at.txt b/llvm/test/MC/Disassembler/AArch64/armv8.2a-at.txt new file mode 100644 index 00000000000..81841f2c130 --- /dev/null +++ b/llvm/test/MC/Disassembler/AArch64/armv8.2a-at.txt @@ -0,0 +1,9 @@ +# RUN: llvm-mc -triple aarch64-none-linux-gnu -mattr=+v8.2a --disassemble < %s | FileCheck %s +# RUN: llvm-mc -triple aarch64-none-linux-gnu -mattr=-v8.2a --disassemble < %s | FileCheck %s --check-prefix=NO_V82 + +[0x01,0x79,0x08,0xd5] +[0x22,0x79,0x08,0xd5] +# CHECK: at s1e1rp, x1 +# CHECK: at s1e1wp, x2 +# NO_V82: sys #0, c7, c9, #0, x1 +# NO_V82: sys #0, c7, c9, #1, x2 |
