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-rw-r--r--llvm/lib/Target/X86/Disassembler/X86Disassembler.cpp4
-rw-r--r--llvm/unittests/MC/Disassembler.cpp4
2 files changed, 7 insertions, 1 deletions
diff --git a/llvm/lib/Target/X86/Disassembler/X86Disassembler.cpp b/llvm/lib/Target/X86/Disassembler/X86Disassembler.cpp
index 8d0c12e9464..34ea95d418b 100644
--- a/llvm/lib/Target/X86/Disassembler/X86Disassembler.cpp
+++ b/llvm/lib/Target/X86/Disassembler/X86Disassembler.cpp
@@ -203,6 +203,8 @@ static bool isREX(struct InternalInstruction *insn, uint8_t prefix) {
// Consumes all of an instruction's prefix bytes, and marks the
// instruction as having them. Also sets the instruction's default operand,
// address, and other relevant data sizes to report operands correctly.
+//
+// insn must not be empty.
static int readPrefixes(struct InternalInstruction *insn) {
bool isPrefix = true;
uint8_t byte = 0;
@@ -1707,7 +1709,7 @@ MCDisassembler::DecodeStatus X86GenericDisassembler::getInstruction(
Insn.readerCursor = Address;
Insn.mode = fMode;
- if (readPrefixes(&Insn) || readOpcode(&Insn) ||
+ if (Bytes.empty() || readPrefixes(&Insn) || readOpcode(&Insn) ||
getInstructionID(&Insn, MII.get()) || Insn.instructionID == 0 ||
readOperands(&Insn)) {
Size = Insn.readerCursor - Address;
diff --git a/llvm/unittests/MC/Disassembler.cpp b/llvm/unittests/MC/Disassembler.cpp
index cdb344474ca..3f9e6e5501e 100644
--- a/llvm/unittests/MC/Disassembler.cpp
+++ b/llvm/unittests/MC/Disassembler.cpp
@@ -38,6 +38,10 @@ TEST(Disassembler, X86Test) {
unsigned NumBytes = sizeof(Bytes);
unsigned PC = 0;
+ InstSize =
+ LLVMDisasmInstruction(DCR, BytesP, 0, PC, OutString, OutStringSize);
+ EXPECT_EQ(InstSize, 0U);
+
InstSize = LLVMDisasmInstruction(DCR, BytesP, NumBytes, PC, OutString,
OutStringSize);
EXPECT_EQ(InstSize, 1U);
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