diff options
| -rw-r--r-- | llvm/lib/Target/X86/X86ISelLowering.cpp | 9 | ||||
| -rw-r--r-- | llvm/test/CodeGen/X86/combine-and.ll | 4 |
2 files changed, 11 insertions, 2 deletions
diff --git a/llvm/lib/Target/X86/X86ISelLowering.cpp b/llvm/lib/Target/X86/X86ISelLowering.cpp index 47f20a2b456..547250375aa 100644 --- a/llvm/lib/Target/X86/X86ISelLowering.cpp +++ b/llvm/lib/Target/X86/X86ISelLowering.cpp @@ -26661,6 +26661,15 @@ unsigned X86TargetLowering::ComputeNumSignBitsForTargetNode( return Tmp; } + case X86ISD::VSRAI: { + SDValue Src = Op.getOperand(0); + unsigned Tmp = DAG.ComputeNumSignBits(Src, Depth + 1); + unsigned VTBits = Op.getValueType().getScalarSizeInBits(); + APInt ShiftVal = cast<ConstantSDNode>(Op.getOperand(1))->getAPIntValue(); + ShiftVal += Tmp; + return ShiftVal.uge(VTBits) ? VTBits : ShiftVal.getZExtValue(); + } + case X86ISD::PCMPGT: case X86ISD::PCMPEQ: case X86ISD::CMPP: diff --git a/llvm/test/CodeGen/X86/combine-and.ll b/llvm/test/CodeGen/X86/combine-and.ll index 00e5f8f847a..352705b48d9 100644 --- a/llvm/test/CodeGen/X86/combine-and.ll +++ b/llvm/test/CodeGen/X86/combine-and.ll @@ -254,7 +254,7 @@ define <8 x i16> @ashr_mask1_v8i16(<8 x i16> %a0) { ; CHECK-LABEL: ashr_mask1_v8i16: ; CHECK: # BB#0: ; CHECK-NEXT: psraw $15, %xmm0 -; CHECK-NEXT: pand {{.*}}(%rip), %xmm0 +; CHECK-NEXT: psrlw $15, %xmm0 ; CHECK-NEXT: retq %1 = ashr <8 x i16> %a0, <i16 15, i16 15, i16 15, i16 15, i16 15, i16 15, i16 15, i16 15> %2 = and <8 x i16> %1, <i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1> @@ -265,7 +265,7 @@ define <4 x i32> @ashr_mask7_v4i32(<4 x i32> %a0) { ; CHECK-LABEL: ashr_mask7_v4i32: ; CHECK: # BB#0: ; CHECK-NEXT: psrad $31, %xmm0 -; CHECK-NEXT: pand {{.*}}(%rip), %xmm0 +; CHECK-NEXT: psrld $29, %xmm0 ; CHECK-NEXT: retq %1 = ashr <4 x i32> %a0, <i32 31, i32 31, i32 31, i32 31> %2 = and <4 x i32> %1, <i32 7, i32 7, i32 7, i32 7> |
