diff options
| -rw-r--r-- | llvm/docs/GlobalISel.rst | 2 | ||||
| -rw-r--r-- | llvm/include/llvm/Analysis/InstructionPrecedenceTracking.h | 2 | ||||
| -rw-r--r-- | llvm/include/llvm/DebugInfo/PDB/Native/RawTypes.h | 10 | ||||
| -rw-r--r-- | llvm/lib/Analysis/MemoryDependenceAnalysis.cpp | 2 | ||||
| -rw-r--r-- | llvm/lib/CodeGen/LiveDebugVariables.cpp | 2 | ||||
| -rw-r--r-- | llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp | 8 | ||||
| -rw-r--r-- | llvm/lib/IR/Verifier.cpp | 2 | ||||
| -rw-r--r-- | llvm/lib/MC/MCParser/AsmLexer.cpp | 2 | ||||
| -rw-r--r-- | llvm/lib/Target/NVPTX/NVPTXISelLowering.cpp | 2 |
9 files changed, 16 insertions, 16 deletions
diff --git a/llvm/docs/GlobalISel.rst b/llvm/docs/GlobalISel.rst index 8746685491c..90e90f5b9cc 100644 --- a/llvm/docs/GlobalISel.rst +++ b/llvm/docs/GlobalISel.rst @@ -544,7 +544,7 @@ Custom SDNodes Custom SDNodes should be mapped to Target Pseudos using ``GINodeEquiv``. This will cause the instruction selector to import them but you will also need to ensure the target pseudo is introduced to the MIR before the instruction -selector. Any preceeding pass is suitable but the legalizer will be a +selector. Any preceding pass is suitable but the legalizer will be a particularly common choice. ComplexPatterns diff --git a/llvm/include/llvm/Analysis/InstructionPrecedenceTracking.h b/llvm/include/llvm/Analysis/InstructionPrecedenceTracking.h index eb72eac23ec..3c3981066a4 100644 --- a/llvm/include/llvm/Analysis/InstructionPrecedenceTracking.h +++ b/llvm/include/llvm/Analysis/InstructionPrecedenceTracking.h @@ -92,7 +92,7 @@ public: /// example, throwing calls and guards do not always do this. If we need to know /// for sure that some instruction is guaranteed to execute if the given block /// is reached, then we need to make sure that there is no implicit control flow -/// instruction (ICFI) preceeding it. For example, this check is required if we +/// instruction (ICFI) preceding it. For example, this check is required if we /// perform PRE moving non-speculable instruction to other place. class ImplicitControlFlowTracking : public InstructionPrecedenceTracking { public: diff --git a/llvm/include/llvm/DebugInfo/PDB/Native/RawTypes.h b/llvm/include/llvm/DebugInfo/PDB/Native/RawTypes.h index 84b0cb39bf1..e2d4ae44ee6 100644 --- a/llvm/include/llvm/DebugInfo/PDB/Native/RawTypes.h +++ b/llvm/include/llvm/DebugInfo/PDB/Native/RawTypes.h @@ -176,7 +176,7 @@ struct DbiStreamHeader { }; static_assert(sizeof(DbiStreamHeader) == 64, "Invalid DbiStreamHeader size!"); -/// The header preceeding the File Info Substream of the DBI stream. +/// The header preceding the File Info Substream of the DBI stream. struct FileInfoSubstreamHeader { /// Total # of modules, should match number of records in the ModuleInfo /// substream. @@ -207,7 +207,7 @@ struct ModInfoFlags { static const uint16_t TypeServerIndexShift = 8; }; -/// The header preceeding each entry in the Module Info substream of the DBI +/// The header preceding each entry in the Module Info substream of the DBI /// stream. Corresponds to the type MODI in the reference implementation. struct ModuleInfoHeader { /// Currently opened module. This field is a pointer in the reference @@ -272,7 +272,7 @@ struct PublicsStreamHeader { support::ulittle32_t NumSections; }; -// The header preceeding the global TPI stream. +// The header preceding the global TPI stream. // This corresponds to `HDR` in PDB/dbi/tpi.h. struct TpiStreamHeader { struct EmbeddedBuf { @@ -300,7 +300,7 @@ struct TpiStreamHeader { const uint32_t MinTpiHashBuckets = 0x1000; const uint32_t MaxTpiHashBuckets = 0x40000; -/// The header preceeding the global PDB Stream (Stream 1) +/// The header preceding the global PDB Stream (Stream 1) struct InfoStreamHeader { support::ulittle32_t Version; support::ulittle32_t Signature; @@ -308,7 +308,7 @@ struct InfoStreamHeader { codeview::GUID Guid; }; -/// The header preceeding the /names stream. +/// The header preceding the /names stream. struct PDBStringTableHeader { support::ulittle32_t Signature; // PDBStringTableSignature support::ulittle32_t HashVersion; // 1 or 2 diff --git a/llvm/lib/Analysis/MemoryDependenceAnalysis.cpp b/llvm/lib/Analysis/MemoryDependenceAnalysis.cpp index 98c3ae40d47..7b638ed135e 100644 --- a/llvm/lib/Analysis/MemoryDependenceAnalysis.cpp +++ b/llvm/lib/Analysis/MemoryDependenceAnalysis.cpp @@ -672,7 +672,7 @@ MemDepResult MemoryDependenceResults::getSimplePointerDependencyFrom( // A release fence requires that all stores complete before it, but does // not prevent the reordering of following loads or stores 'before' the // fence. As a result, we look past it when finding a dependency for - // loads. DSE uses this to find preceeding stores to delete and thus we + // loads. DSE uses this to find preceding stores to delete and thus we // can't bypass the fence if the query instruction is a store. if (FenceInst *FI = dyn_cast<FenceInst>(Inst)) if (isLoad && FI->getOrdering() == AtomicOrdering::Release) diff --git a/llvm/lib/CodeGen/LiveDebugVariables.cpp b/llvm/lib/CodeGen/LiveDebugVariables.cpp index f5afa15bdb2..eeddba5037a 100644 --- a/llvm/lib/CodeGen/LiveDebugVariables.cpp +++ b/llvm/lib/CodeGen/LiveDebugVariables.cpp @@ -619,7 +619,7 @@ bool LDVImpl::handleDebugValue(MachineInstr &MI, SlotIndex Idx) { } else { // The DBG_VALUE is only valid if either Reg is live out from Idx, or Reg // is defined dead at Idx (where Idx is the slot index for the instruction - // preceeding the DBG_VALUE). + // preceding the DBG_VALUE). const LiveInterval &LI = LIS->getInterval(Reg); LiveQueryResult LRQ = LI.Query(Idx); if (!LRQ.valueOutOrDead()) { diff --git a/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp b/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp index c118dfffed2..07214d73fa4 100644 --- a/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp +++ b/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp @@ -13978,7 +13978,7 @@ CheckForMaskedLoad(SDValue V, SDValue Ptr, SDValue Chain) { if (NotMaskTZ && NotMaskTZ/8 % MaskedBytes) return Result; // For narrowing to be valid, it must be the case that the load the - // immediately preceeding memory operation before the store. + // immediately preceding memory operation before the store. if (LD == Chain.getNode()) ; // ok. else if (Chain->getOpcode() == ISD::TokenFactor && @@ -15429,7 +15429,7 @@ SDValue DAGCombiner::visitSTORE(SDNode *N) { const BaseIndexOffset ChainBase = BaseIndexOffset::match(ST1, DAG); unsigned STByteSize = ST->getMemoryVT().getSizeInBits() / 8; unsigned ChainByteSize = ST1->getMemoryVT().getSizeInBits() / 8; - // If this is a store who's preceeding store to a subset of the current + // If this is a store who's preceding store to a subset of the current // location and no one other node is chained to that store we can // effectively drop the store. Do not remove stores to undef as they may // be used as data sinks. @@ -15438,8 +15438,8 @@ SDValue DAGCombiner::visitSTORE(SDNode *N) { return SDValue(); } - // If ST stores to a subset of preceeding store's write set, we may be - // able to fold ST's value into the preceeding stored value. As we know + // If ST stores to a subset of preceding store's write set, we may be + // able to fold ST's value into the preceding stored value. As we know // the other uses of ST1's chain are unconcerned with ST, this folding // will not affect those nodes. int64_t Offset; diff --git a/llvm/lib/IR/Verifier.cpp b/llvm/lib/IR/Verifier.cpp index f7d22ec74a8..55d3a323610 100644 --- a/llvm/lib/IR/Verifier.cpp +++ b/llvm/lib/IR/Verifier.cpp @@ -3918,7 +3918,7 @@ void Verifier::verifyDominatesUse(Instruction &I, unsigned i) { } // Quick check whether the def has already been encountered in the same block. - // PHI nodes are not checked to prevent accepting preceeding PHIs, because PHI + // PHI nodes are not checked to prevent accepting preceding PHIs, because PHI // uses are defined to happen on the incoming edge, not at the instruction. // // FIXME: If this operand is a MetadataAsValue (wrapping a LocalAsMetadata) diff --git a/llvm/lib/MC/MCParser/AsmLexer.cpp b/llvm/lib/MC/MCParser/AsmLexer.cpp index 88a131efe10..d21bc64c342 100644 --- a/llvm/lib/MC/MCParser/AsmLexer.cpp +++ b/llvm/lib/MC/MCParser/AsmLexer.cpp @@ -556,7 +556,7 @@ AsmToken AsmLexer::LexToken() { AsmToken TokenBuf[2]; MutableArrayRef<AsmToken> Buf(TokenBuf, 2); size_t num = peekTokens(Buf, true); - // There cannot be a space preceeding this + // There cannot be a space preceding this if (IsAtStartOfLine && num == 2 && TokenBuf[0].is(AsmToken::Integer) && TokenBuf[1].is(AsmToken::String)) { CurPtr = TokStart; // reset curPtr; diff --git a/llvm/lib/Target/NVPTX/NVPTXISelLowering.cpp b/llvm/lib/Target/NVPTX/NVPTXISelLowering.cpp index 21c0c8c46cb..2e955f89049 100644 --- a/llvm/lib/Target/NVPTX/NVPTXISelLowering.cpp +++ b/llvm/lib/Target/NVPTX/NVPTXISelLowering.cpp @@ -1502,7 +1502,7 @@ SDValue NVPTXTargetLowering::LowerCall(TargetLowering::CallLoweringInfo &CLI, for (unsigned j = 0, je = VTs.size(); j != je; ++j) { // New store. if (VectorInfo[j] & PVF_FIRST) { - assert(StoreOperands.empty() && "Unfinished preceeding store."); + assert(StoreOperands.empty() && "Unfinished preceding store."); StoreOperands.push_back(Chain); StoreOperands.push_back(DAG.getConstant(paramCount, dl, MVT::i32)); StoreOperands.push_back(DAG.getConstant(Offsets[j], dl, MVT::i32)); |
