diff options
| -rw-r--r-- | llvm/lib/Target/AArch64/AArch64RegisterBankInfo.cpp | 10 | ||||
| -rw-r--r-- | llvm/test/CodeGen/AArch64/GlobalISel/arm64-regbankselect.mir | 18 |
2 files changed, 15 insertions, 13 deletions
diff --git a/llvm/lib/Target/AArch64/AArch64RegisterBankInfo.cpp b/llvm/lib/Target/AArch64/AArch64RegisterBankInfo.cpp index 5289063ca2b..9940a74d7a8 100644 --- a/llvm/lib/Target/AArch64/AArch64RegisterBankInfo.cpp +++ b/llvm/lib/Target/AArch64/AArch64RegisterBankInfo.cpp @@ -611,7 +611,15 @@ AArch64RegisterBankInfo::getInstrMapping(const MachineInstr &MI) const { if (!VReg) break; MachineInstr *DefMI = MRI.getVRegDef(VReg); - if (isPreISelGenericFloatingPointOpcode(DefMI->getOpcode())) + unsigned DefOpc = DefMI->getOpcode(); + if (isPreISelGenericFloatingPointOpcode(DefOpc) || + // Check if we come from a copy-like instruction with + // floating point constraints. In that case, we are still + // fed by fp instructions, but indirectly + // (e.g., through ABI copies). + ((DefOpc == TargetOpcode::COPY || DefMI->isPHI()) && + getRegBank(DefMI->getOperand(0).getReg(), MRI, TRI) == + &AArch64::FPRRegBank)) OpRegBankIdx[0] = PMI_FirstFPR; break; } diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/arm64-regbankselect.mir b/llvm/test/CodeGen/AArch64/GlobalISel/arm64-regbankselect.mir index a5df93b4926..aace553af2d 100644 --- a/llvm/test/CodeGen/AArch64/GlobalISel/arm64-regbankselect.mir +++ b/llvm/test/CodeGen/AArch64/GlobalISel/arm64-regbankselect.mir @@ -911,26 +911,20 @@ body: | ... --- -# This test tries to mix 16-bit types on fpr with 32-bit types on gpr. -# The problem when doing that is that switching from fpr to gpr requires -# more than just a plain COPY. -# In this specific case, currently we map the ABI copy from h0 to fpr, -# then, the fast mapping takes GPR for store and the size of the storage -# gets bumped to 32-bit. +# Make sure we properly detect fp types through copies. +# In that example, the copy comes from an ABI lowering of a fp type. # CHECK-LABEL: name: passFp16ViaAllocas # CHECK: registers: # CHECK: - { id: 0, class: fpr, preferred-register: '' } # CHECK: - { id: 1, class: gpr, preferred-register: '' } # CHECK: - { id: 2, class: gpr, preferred-register: '' } -# CHECK: - { id: 3, class: gpr, preferred-register: '' } # # CHECK: %0:fpr(s16) = COPY %h0 # CHECK-NEXT: %1:gpr(p0) = G_FRAME_INDEX %stack.0.p.addr -# Currently the default mapping we provide for store does not -# consider fpr for s16, unless they are produced by floating point -# operation. Thus, we have to repair the assignment. -# CHECK-NEXT: %3:gpr(s16) = COPY %0(s16) -# CHECK-NEXT: G_STORE %3(s16), %1(p0) :: (store 2 into %ir.p.addr) +# If we didn't look through the copy for %0, the default mapping +# would have been on GPR and we would have to insert a copy to move +# the value away from FPR (h0). +# CHECK-NEXT: G_STORE %0(s16), %1(p0) :: (store 2 into %ir.p.addr) # CHECK-NEXT: %2:gpr(s16) = G_LOAD %1(p0) :: (load 2 from %ir.p.addr) # CHECK-NEXT: %h0 = COPY %2(s16) name: passFp16ViaAllocas |
