diff options
| -rw-r--r-- | llvm/lib/Target/ARM/AsmParser/ARMAsmParser.cpp | 8 | ||||
| -rw-r--r-- | llvm/test/MC/ARM/thumb-load-store-multiple.s | 16 |
2 files changed, 15 insertions, 9 deletions
diff --git a/llvm/lib/Target/ARM/AsmParser/ARMAsmParser.cpp b/llvm/lib/Target/ARM/AsmParser/ARMAsmParser.cpp index 2c2860dad8d..6a00b28f37a 100644 --- a/llvm/lib/Target/ARM/AsmParser/ARMAsmParser.cpp +++ b/llvm/lib/Target/ARM/AsmParser/ARMAsmParser.cpp @@ -190,7 +190,7 @@ class ARMAsmParser : public MCTargetAsmParser { } bool validatetLDMRegList(MCInst Inst, const OperandVector &Operands, - unsigned ListNo, bool IsPop = false); + unsigned ListNo, bool IsARPop = false); bool validatetSTMRegList(MCInst Inst, const OperandVector &Operands, unsigned ListNo); @@ -6027,7 +6027,7 @@ static bool instIsBreakpoint(const MCInst &Inst) { bool ARMAsmParser::validatetLDMRegList(MCInst Inst, const OperandVector &Operands, - unsigned ListNo, bool IsPop) { + unsigned ListNo, bool IsARPop) { const ARMOperand &Op = static_cast<const ARMOperand &>(*Operands[ListNo]); bool HasWritebackToken = Op.isToken() && Op.getToken() == "!"; @@ -6035,7 +6035,7 @@ bool ARMAsmParser::validatetLDMRegList(MCInst Inst, bool ListContainsLR = listContainsReg(Inst, ListNo, ARM::LR); bool ListContainsPC = listContainsReg(Inst, ListNo, ARM::PC); - if (!IsPop && ListContainsSP) + if (!IsARPop && ListContainsSP) return Error(Operands[ListNo + HasWritebackToken]->getStartLoc(), "SP may not be in the register list"); else if (ListContainsPC && ListContainsLR) @@ -6338,7 +6338,7 @@ bool ARMAsmParser::validateInstruction(MCInst &Inst, !isThumbTwo()) return Error(Operands[2]->getStartLoc(), "registers must be in range r0-r7 or pc"); - if (validatetLDMRegList(Inst, Operands, 2, /*IsPop=*/true)) + if (validatetLDMRegList(Inst, Operands, 2, !isMClass())) return true; break; } diff --git a/llvm/test/MC/ARM/thumb-load-store-multiple.s b/llvm/test/MC/ARM/thumb-load-store-multiple.s index 60d2ec3f733..6958450df07 100644 --- a/llvm/test/MC/ARM/thumb-load-store-multiple.s +++ b/llvm/test/MC/ARM/thumb-load-store-multiple.s @@ -1,12 +1,16 @@ @ RUN: not llvm-mc -triple thumbv7-eabi -filetype asm -o - %s 2>&1 \ @ RUN: | FileCheck %s +@ RUN: not llvm-mc -triple thumbv7a-eabi -filetype asm -o - %s 2>&1 \ +@ RUN: | FileCheck --check-prefix=CHECK --check-prefix=CHECK-V7A %s +@ RUN: not llvm-mc -triple thumbv7m-eabi -filetype asm -o - %s 2>&1 \ +@ RUN: | FileCheck --check-prefix=CHECK --check-prefix=CHECK-V7M %s .syntax unified .thumb .global ldm .type ldm,%function -ldb: +ldm: ldm r0!, {r1, sp} @ CHECK: error: SP may not be in the register list @ CHECK: ldm r0!, {r1, sp} @@ -27,7 +31,7 @@ ldb: ldmdb: ldmdb r0!, {r1, sp} @ CHECK: error: SP may not be in the register list - ldm r0!, {lr, pc} + ldmdb r0!, {lr, pc} @ error: PC and LR may not be in the register list simultaneously itt eq ldmeq r0!, {r1, pc} @@ -63,12 +67,14 @@ push: @ CHECK: error: SP may not be in the register list push {pc} @ CHECK: error: PC may not be in the register list - push {sp,pc} + push {sp, pc} @ CHECK: error: SP and PC may not be in the register list .global pop .type pop,%function pop: + pop {sp} +@ CHECK-V7M: error: SP may not be in the register list pop {lr, pc} @ CHECK: error: PC and LR may not be in the register list simultaneously @ CHECK: pop {lr, pc} @@ -84,9 +90,9 @@ pop: .type valid,%function valid: pop {sp} -@ CHECK: ldr sp, [sp], #4 +@ CHECK-V7A: ldr sp, [sp], #4 pop {sp, pc} -@ CHECK: pop.w {sp, pc} +@ CHECK-V7A: pop.w {sp, pc} push.w {r0} @ CHECK: str r0, [sp, #-4] pop.w {r0} |
