diff options
| -rw-r--r-- | llvm/include/llvm/CodeGen/GlobalISel/Utils.h | 3 | ||||
| -rw-r--r-- | llvm/lib/CodeGen/GlobalISel/Utils.cpp | 16 | ||||
| -rw-r--r-- | llvm/lib/Target/AArch64/AArch64CallLowering.cpp | 3 | ||||
| -rw-r--r-- | llvm/lib/Target/ARM/ARMCallLowering.cpp | 2 | ||||
| -rw-r--r-- | llvm/lib/Target/X86/X86CallLowering.cpp | 3 |
5 files changed, 14 insertions, 13 deletions
diff --git a/llvm/include/llvm/CodeGen/GlobalISel/Utils.h b/llvm/include/llvm/CodeGen/GlobalISel/Utils.h index a5859938e5f..36cf652761d 100644 --- a/llvm/include/llvm/CodeGen/GlobalISel/Utils.h +++ b/llvm/include/llvm/CodeGen/GlobalISel/Utils.h @@ -21,6 +21,7 @@ namespace llvm { class MachineFunction; class MachineInstr; +class MachineOperand; class MachineOptimizationRemarkEmitter; class MachineOptimizationRemarkMissed; class MachineRegisterInfo; @@ -57,7 +58,7 @@ unsigned constrainOperandRegClass(const MachineFunction &MF, const TargetInstrInfo &TII, const RegisterBankInfo &RBI, MachineInstr &InsertPt, const MCInstrDesc &II, - unsigned Reg, unsigned OpIdx); + const MachineOperand &RegMO, unsigned OpIdx); /// Mutate the newly-selected instruction \p I to constrain its (possibly /// generic) virtual register operands to the instruction's register class. diff --git a/llvm/lib/CodeGen/GlobalISel/Utils.cpp b/llvm/lib/CodeGen/GlobalISel/Utils.cpp index 35ad433a97d..d75964a0773 100644 --- a/llvm/lib/CodeGen/GlobalISel/Utils.cpp +++ b/llvm/lib/CodeGen/GlobalISel/Utils.cpp @@ -42,23 +42,25 @@ unsigned llvm::constrainRegToClass(MachineRegisterInfo &MRI, return Reg; } - unsigned llvm::constrainOperandRegClass( const MachineFunction &MF, const TargetRegisterInfo &TRI, MachineRegisterInfo &MRI, const TargetInstrInfo &TII, const RegisterBankInfo &RBI, MachineInstr &InsertPt, const MCInstrDesc &II, - unsigned Reg, unsigned OpIdx) { + const MachineOperand &RegMO, unsigned OpIdx) { + unsigned Reg = RegMO.getReg(); // Assume physical registers are properly constrained. assert(TargetRegisterInfo::isVirtualRegister(Reg) && "PhysReg not implemented"); const TargetRegisterClass *RegClass = TII.getRegClass(II, OpIdx, &TRI, MF); // Some of the target independent instructions, like COPY, may not impose any - // register class constraints on some of their operands: + // register class constraints on some of their operands: If it's a use, we can + // skip constraining as the instruction defining the register would constrain + // it. if (!RegClass) { - assert(!isTargetSpecificOpcode(II.getOpcode()) && - "Only target independent instructions are allowed to have operands " - "with no register class constraints"); + assert((!isTargetSpecificOpcode(II.getOpcode()) || RegMO.isUse()) && + "Register class constraint is required unless either the " + "instruction is target independent or the operand is a use"); // FIXME: Just bailing out like this here could be not enough, unless we // expect the users of this function to do the right thing for PHIs and // COPY: @@ -108,7 +110,7 @@ bool llvm::constrainSelectedInstRegOperands(MachineInstr &I, // insert COPYs if that's impossible. // constrainOperandRegClass does that for us. MO.setReg(constrainOperandRegClass(MF, TRI, MRI, TII, RBI, I, I.getDesc(), - Reg, OpI)); + MO, OpI)); // Tie uses to defs as indicated in MCInstrDesc if this hasn't already been // done. diff --git a/llvm/lib/Target/AArch64/AArch64CallLowering.cpp b/llvm/lib/Target/AArch64/AArch64CallLowering.cpp index 08152c0d83d..2de20a56373 100644 --- a/llvm/lib/Target/AArch64/AArch64CallLowering.cpp +++ b/llvm/lib/Target/AArch64/AArch64CallLowering.cpp @@ -369,8 +369,7 @@ bool AArch64CallLowering::lowerCall(MachineIRBuilder &MIRBuilder, if (Callee.isReg()) MIB->getOperand(0).setReg(constrainOperandRegClass( MF, *TRI, MRI, *MF.getSubtarget().getInstrInfo(), - *MF.getSubtarget().getRegBankInfo(), *MIB, MIB->getDesc(), - Callee.getReg(), 0)); + *MF.getSubtarget().getRegBankInfo(), *MIB, MIB->getDesc(), Callee, 0)); // Finally we can copy the returned value back into its virtual-register. In // symmetry with the arugments, the physical register must be an diff --git a/llvm/lib/Target/ARM/ARMCallLowering.cpp b/llvm/lib/Target/ARM/ARMCallLowering.cpp index eab4b3b13f3..7771521f8e3 100644 --- a/llvm/lib/Target/ARM/ARMCallLowering.cpp +++ b/llvm/lib/Target/ARM/ARMCallLowering.cpp @@ -521,7 +521,7 @@ bool ARMCallLowering::lowerCall(MachineIRBuilder &MIRBuilder, if (CalleeReg && !TRI->isPhysicalRegister(CalleeReg)) MIB->getOperand(0).setReg(constrainOperandRegClass( MF, *TRI, MRI, *STI.getInstrInfo(), *STI.getRegBankInfo(), - *MIB.getInstr(), MIB->getDesc(), CalleeReg, 0)); + *MIB.getInstr(), MIB->getDesc(), Callee, 0)); } SmallVector<ArgInfo, 8> ArgInfos; diff --git a/llvm/lib/Target/X86/X86CallLowering.cpp b/llvm/lib/Target/X86/X86CallLowering.cpp index 80dd872d1ba..231b69e8c90 100644 --- a/llvm/lib/Target/X86/X86CallLowering.cpp +++ b/llvm/lib/Target/X86/X86CallLowering.cpp @@ -438,8 +438,7 @@ bool X86CallLowering::lowerCall(MachineIRBuilder &MIRBuilder, if (Callee.isReg()) MIB->getOperand(0).setReg(constrainOperandRegClass( MF, *TRI, MRI, *MF.getSubtarget().getInstrInfo(), - *MF.getSubtarget().getRegBankInfo(), *MIB, MIB->getDesc(), - Callee.getReg(), 0)); + *MF.getSubtarget().getRegBankInfo(), *MIB, MIB->getDesc(), Callee, 0)); // Finally we can copy the returned value back into its virtual-register. In // symmetry with the arguments, the physical register must be an |
