9 files changed, 166 insertions, 2 deletions
diff --git a/clang/include/clang/Basic/BuiltinsX86.def b/clang/include/clang/Basic/BuiltinsX86.def
index cfa38fbff15..3e39e836730 100644
--- a/clang/include/clang/Basic/BuiltinsX86.def
+++ b/clang/include/clang/Basic/BuiltinsX86.def
@@ -641,6 +641,15 @@ BUILTIN(__builtin_ia32_pdep_di, "ULLiULLiULLi", "")
 BUILTIN(__builtin_ia32_pext_si, "UiUiUi", "")
 BUILTIN(__builtin_ia32_pext_di, "ULLiULLiULLi", "")
 
+// SHA
+BUILTIN(__builtin_ia32_sha1rnds4, "V4iV4iV4iIc", "")
+BUILTIN(__builtin_ia32_sha1nexte, "V4iV4iV4i", "")
+BUILTIN(__builtin_ia32_sha1msg1, "V4iV4iV4i", "")
+BUILTIN(__builtin_ia32_sha1msg2, "V4iV4iV4i", "")
+BUILTIN(__builtin_ia32_sha256rnds2, "V4iV4iV4iV4i", "")
+BUILTIN(__builtin_ia32_sha256msg1, "V4iV4iV4i", "")
+BUILTIN(__builtin_ia32_sha256msg2, "V4iV4iV4i", "")
+
 // FMA4
 BUILTIN(__builtin_ia32_vfmaddps, "V4fV4fV4fV4f", "")
 BUILTIN(__builtin_ia32_vfmaddpd, "V2dV2dV2dV2d", "")
diff --git a/clang/include/clang/Driver/Options.td b/clang/include/clang/Driver/Options.td
index 95dd607c1c4..2f0d3a283f5 100644
--- a/clang/include/clang/Driver/Options.td
+++ b/clang/include/clang/Driver/Options.td
@@ -981,6 +981,7 @@ def mno_f16c : Flag<["-"], "mno-f16c">, Group<m_x86_Features_Group>;
 def mno_rtm : Flag<["-"], "mno-rtm">, Group<m_x86_Features_Group>;
 def mno_prfchw : Flag<["-"], "mno-prfchw">, Group<m_x86_Features_Group>;
 def mno_rdseed : Flag<["-"], "mno-rdseed">, Group<m_x86_Features_Group>;
+def mno_sha : Flag<["-"], "mno-sha">, Group<m_x86_Features_Group>;
 
 def munaligned_access : Flag<["-"], "munaligned-access">, Group<m_arm_Features_Group>,
   HelpText<"Allow memory accesses to be unaligned (ARM only)">;
@@ -1039,6 +1040,7 @@ def mf16c : Flag<["-"], "mf16c">, Group<m_x86_Features_Group>;
 def mrtm : Flag<["-"], "mrtm">, Group<m_x86_Features_Group>;
 def mprfchw : Flag<["-"], "mprfchw">, Group<m_x86_Features_Group>;
 def mrdseed : Flag<["-"], "mrdseed">, Group<m_x86_Features_Group>;
+def msha : Flag<["-"], "msha">, Group<m_x86_Features_Group>;
 def mips16 : Flag<["-"], "mips16">, Group<m_Group>;
 def mno_mips16 : Flag<["-"], "mno-mips16">, Group<m_Group>;
 def mmicromips : Flag<["-"], "mmicromips">, Group<m_Group>;
diff --git a/clang/lib/Basic/Targets.cpp b/clang/lib/Basic/Targets.cpp
index 3e54c12c19b..2f4aeb93bef 100644
--- a/clang/lib/Basic/Targets.cpp
+++ b/clang/lib/Basic/Targets.cpp
@@ -1589,6 +1589,7 @@ class X86TargetInfo : public TargetInfo {
   bool HasFMA;
   bool HasF16C;
   bool HasAVX512CD, HasAVX512ER, HasAVX512PF;
+  bool HasSHA;
 
   /// \brief Enumeration of all of the X86 CPUs supported by Clang.
   ///
@@ -1749,7 +1750,7 @@ public:
         HasRDRND(false), HasBMI(false), HasBMI2(false), HasPOPCNT(false),
         HasRTM(false), HasPRFCHW(false), HasRDSEED(false), HasFMA(false),
         HasF16C(false), HasAVX512CD(false), HasAVX512ER(false),
-        HasAVX512PF(false), CPU(CK_Generic), FPMath(FP_Default) {
+        HasAVX512PF(false), HasSHA(false), CPU(CK_Generic), FPMath(FP_Default) {
     BigEndian = false;
     LongDoubleFormat = &llvm::APFloat::x87DoubleExtended;
   }
@@ -2166,7 +2167,8 @@ void X86TargetInfo::setSSELevel(llvm::StringMap<bool> &Features,
   case SSE1:
     Features["sse"] = false;
   case SSE2:
-    Features["sse2"] = Features["pclmul"] = Features["aes"] = false;
+    Features["sse2"] = Features["pclmul"] = Features["aes"] =
+      Features["sha"] = false;
   case SSE3:
     Features["sse3"] = false;
     setXOPLevel(Features, NoXOP, false);
@@ -2297,6 +2299,9 @@ void X86TargetInfo::setFeatureEnabledImpl(llvm::StringMap<bool> &Features,
   } else if (Name == "f16c") {
     if (Enabled)
       setSSELevel(Features, AVX, Enabled);
+  } else if (Name == "sha") {
+    if (Enabled)
+      setSSELevel(Features, SSE2, Enabled);
   }
 }
 
@@ -2387,6 +2392,11 @@ bool X86TargetInfo::HandleTargetFeatures(std::vector<std::string> &Features,
       continue;
     }
 
+    if (Feature == "sha") {
+      HasSHA = true;
+      continue;
+    }
+
     assert(Features[i][0] == '+' && "Invalid target feature!");
     X86SSEEnum Level = llvm::StringSwitch<X86SSEEnum>(Feature)
       .Case("avx512f", AVX512F)
@@ -2656,6 +2666,9 @@ void X86TargetInfo::getTargetDefines(const LangOptions &Opts,
   if (HasAVX512PF)
     Builder.defineMacro("__AVX512PF__");
 
+  if (HasSHA)
+    Builder.defineMacro("__SHA__");
+
   // Each case falls through to the previous one here.
   switch (SSELevel) {
   case AVX512F:
@@ -2746,6 +2759,7 @@ bool X86TargetInfo::hasFeature(StringRef Feature) const {
       .Case("rtm", HasRTM)
       .Case("prfchw", HasPRFCHW)
       .Case("rdseed", HasRDSEED)
+      .Case("sha", HasSHA)
       .Case("sse", SSELevel >= SSE1)
       .Case("sse2", SSELevel >= SSE2)
       .Case("sse3", SSELevel >= SSE3)
diff --git a/clang/lib/Headers/CMakeLists.txt b/clang/lib/Headers/CMakeLists.txt
index fb2ab8b6393..34abea9ed0d 100644
--- a/clang/lib/Headers/CMakeLists.txt
+++ b/clang/lib/Headers/CMakeLists.txt
@@ -24,6 +24,7 @@ set(files
   prfchwintrin.h
   rdseedintrin.h
   rtmintrin.h
+  shaintrin.h
   smmintrin.h
   stdalign.h
   stdarg.h
diff --git a/clang/lib/Headers/shaintrin.h b/clang/lib/Headers/shaintrin.h
new file mode 100644
index 00000000000..934b4e7c917
--- /dev/null
+++ b/clang/lib/Headers/shaintrin.h
@@ -0,0 +1,74 @@
+/*===---- shaintrin.h - SHA intrinsics -------------------------------------===
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
+ * of this software and associated documentation files (the "Software"), to deal
+ * in the Software without restriction, including without limitation the rights
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+ * copies of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+ * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+ * THE SOFTWARE.
+ *
+ *===-----------------------------------------------------------------------===
+ */
+
+#ifndef __X86INTRIN_H
+#error "Never use <shaintrin.h> directly; include <x86intrin.h> instead."
+#endif
+
+#ifndef __SHAINTRIN_H
+#define __SHAINTRIN_H
+
+#if !defined (__SHA__)
+#  error "SHA instructions not enabled"
+#endif
+
+#define _mm_sha1rnds4_epu32(V1, V2, M) __extension__ ({ \
+  __builtin_ia32_sha1rnds4((V1), (V2), (M)); })
+
+static __inline__ __m128i __attribute__((__always_inline__, __nodebug__))
+_mm_sha1nexte_epu32(__m128i __X, __m128i __Y)
+{
+  return __builtin_ia32_sha1nexte(__X, __Y);
+}
+
+static __inline__ __m128i __attribute__((__always_inline__, __nodebug__))
+_mm_sha1msg1_epu32(__m128i __X, __m128i __Y)
+{
+  return __builtin_ia32_sha1msg1(__X, __Y);
+}
+
+static __inline__ __m128i __attribute__((__always_inline__, __nodebug__))
+_mm_sha1msg2_epu32(__m128i __X, __m128i __Y)
+{
+  return __builtin_ia32_sha1msg2(__X, __Y);
+}
+
+static __inline__ __m128i __attribute__((__always_inline__, __nodebug__))
+_mm_sha256rnds2_epu32(__m128i __X, __m128i __Y, __m128i __Z)
+{
+  return __builtin_ia32_sha256rnds2(__X, __Y, __Z);
+}
+
+static __inline__ __m128i __attribute__((__always_inline__, __nodebug__))
+_mm_sha256msg1_epu32(__m128i __X, __m128i __Y)
+{
+  return __builtin_ia32_sha256msg1(__X, __Y);
+}
+
+static __inline__ __m128i __attribute__((__always_inline__, __nodebug__))
+_mm_sha256msg2_epu32(__m128i __X, __m128i __Y)
+{
+  return __builtin_ia32_sha256msg2(__X, __Y);
+}
+
+#endif /* __SHAINTRIN_H */
diff --git a/clang/lib/Headers/x86intrin.h b/clang/lib/Headers/x86intrin.h
index 94fbe2fe234..b0c583f899a 100644
--- a/clang/lib/Headers/x86intrin.h
+++ b/clang/lib/Headers/x86intrin.h
@@ -70,6 +70,10 @@
 #include <f16cintrin.h>
 #endif
 
+ #ifdef __SHA__
+ #include <shaintrin.h>
+ #endif
+
 // FIXME: LWP
 
 #endif /* __X86INTRIN_H */
diff --git a/clang/test/CodeGen/builtins-x86.c b/clang/test/CodeGen/builtins-x86.c
index fcf1512ca16..9e78235d374 100644
--- a/clang/test/CodeGen/builtins-x86.c
+++ b/clang/test/CodeGen/builtins-x86.c
@@ -491,5 +491,13 @@ void f0() {
   tmp_V2f = __builtin_ia32_pi2fw(tmp_V2i);
   tmp_V2f = __builtin_ia32_pswapdsf(tmp_V2f);
   tmp_V2i = __builtin_ia32_pswapdsi(tmp_V2i);
+
+  tmp_V4i = __builtin_ia32_sha1rnds4(tmp_V4i, tmp_V4i, imm_i);
+  tmp_V4i = __builtin_ia32_sha1nexte(tmp_V4i, tmp_V4i);
+  tmp_V4i = __builtin_ia32_sha1msg1(tmp_V4i, tmp_V4i);
+  tmp_V4i = __builtin_ia32_sha1msg2(tmp_V4i, tmp_V4i);
+  tmp_V4i = __builtin_ia32_sha256rnds2(tmp_V4i, tmp_V4i, tmp_V4i);
+  tmp_V4i = __builtin_ia32_sha256msg1(tmp_V4i, tmp_V4i);
+  tmp_V4i = __builtin_ia32_sha256msg2(tmp_V4i, tmp_V4i);
 #endif
 }
diff --git a/clang/test/CodeGen/sha-builtins.c b/clang/test/CodeGen/sha-builtins.c
new file mode 100644
index 00000000000..ba1a4807037
--- /dev/null
+++ b/clang/test/CodeGen/sha-builtins.c
@@ -0,0 +1,35 @@
+// RUN: %clang_cc1 %s -O3 -triple=x86_64-unknown-unknown -target-feature +sha -emit-llvm -o - | FileCheck %s
+
+// Don't include mm_malloc.h, it's system specific.
+#define __MM_MALLOC_H
+
+#include <x86intrin.h>
+
+__m128i test_sha1rnds4(__m128i a, __m128i b) {
+  // CHECK: call <4 x i32> @llvm.x86.sha1rnds4
+  return _mm_sha1rnds4_epu32(a, b, 8);
+}
+__m128i test_sha1nexte(__m128i a, __m128i b) {
+  // CHECK: call <4 x i32> @llvm.x86.sha1nexte
+  return _mm_sha1nexte_epu32(a, b);
+}
+__m128i test_sha1msg1(__m128i a, __m128i b) {
+  // CHECK: call <4 x i32> @llvm.x86.sha1msg1
+  return _mm_sha1msg1_epu32(a, b);
+}
+__m128i test_sha1msg2(__m128i a, __m128i b) {
+  // CHECK: call <4 x i32> @llvm.x86.sha1msg2
+  return _mm_sha1msg2_epu32(a, b);
+}
+__m128i test_sha256rnds2(__m128i a, __m128i b, __m128i c) {
+  // CHECK: call <4 x i32> @llvm.x86.sha256rnds2
+  return _mm_sha256rnds2_epu32(a, b, c);
+}
+__m128i test_sha256msg1(__m128i a, __m128i b) {
+  // CHECK: call <4 x i32> @llvm.x86.sha256msg1
+  return _mm_sha256msg1_epu32(a, b);
+}
+__m128i test_sha256msg2(__m128i a, __m128i b) {
+  // CHECK: call <4 x i32> @llvm.x86.sha256msg2
+  return _mm_sha256msg2_epu32(a, b);
+}
+\ No newline at end of file
diff --git a/clang/test/Preprocessor/x86_target_features.c b/clang/test/Preprocessor/x86_target_features.c
index acffb18e4e0..0cbda296abc 100644
--- a/clang/test/Preprocessor/x86_target_features.c
+++ b/clang/test/Preprocessor/x86_target_features.c
@@ -186,3 +186,20 @@
 // AESNOSSE2-NOT: #define __AES__ 1
 // AESNOSSE2-NOT: #define __SSE2__ 1
 // AESNOSSE2-NOT: #define __SSE3__ 1
+
+// RUN: %clang -target i386-unknown-unknown -march=pentiumpro -msha -x c -E -dM -o - %s | FileCheck --check-prefix=SHA %s
+
+// SHA: #define __SHA__ 1
+// SHA: #define __SSE2__ 1
+// SHA-NOT: #define __SSE3__ 1
+
+// run: %clang -target i386-unknown-unknown -march=pentiumpro -msha -mno-sha -x c -e -dm -o - %s | filecheck --check-prefix=SHANOSHA %s
+
+// SHANOSHA-NOT: #define __SHA__ 1
+// SHANOSHA-NOT: #define __SSE2__ 1
+
+// run: %clang -target i386-unknown-unknown -march=pentiumpro -msha -mno-sse2 -x c -e -dm -o - %s | filecheck --check-prefix=SHANOSSE2 %s
+
+// SHANOSSSE2-NOT: #define __SHA__ 1
+// SHANOSSSE2-NOT: #define __SSE2__ 1
+// SHANOSSSE2-NOT: #define __SSE3__ 1
+\ No newline at end of file