diff options
| -rw-r--r-- | llvm/include/llvm/BinaryFormat/Dwarf.h | 2 | ||||
| -rw-r--r-- | llvm/include/llvm/IR/LLVMContext.h | 4 | ||||
| -rw-r--r-- | llvm/lib/Target/AArch64/AArch64TargetTransformInfo.cpp | 2 | ||||
| -rw-r--r-- | llvm/lib/Target/ARM/AsmParser/ARMAsmParser.cpp | 9 |
4 files changed, 9 insertions, 8 deletions
diff --git a/llvm/include/llvm/BinaryFormat/Dwarf.h b/llvm/include/llvm/BinaryFormat/Dwarf.h index a0e5367b412..ae43076d64e 100644 --- a/llvm/include/llvm/BinaryFormat/Dwarf.h +++ b/llvm/include/llvm/BinaryFormat/Dwarf.h @@ -125,7 +125,7 @@ enum LocationAtom { DW_OP_LLVM_fragment = 0x1000 ///< Only used in LLVM metadata. }; -enum TypeKind { +enum TypeKind : uint8_t { #define HANDLE_DW_ATE(ID, NAME, VERSION, VENDOR) DW_ATE_##NAME = ID, #include "llvm/BinaryFormat/Dwarf.def" DW_ATE_lo_user = 0x80, diff --git a/llvm/include/llvm/IR/LLVMContext.h b/llvm/include/llvm/IR/LLVMContext.h index a95634d32c2..a9ec1a16633 100644 --- a/llvm/include/llvm/IR/LLVMContext.h +++ b/llvm/include/llvm/IR/LLVMContext.h @@ -76,7 +76,7 @@ public: // Pinned metadata names, which always have the same value. This is a // compile-time performance optimization, not a correctness optimization. - enum { + enum : unsigned { MD_dbg = 0, // "dbg" MD_tbaa = 1, // "tbaa" MD_prof = 2, // "prof" @@ -108,7 +108,7 @@ public: /// operand bundle tags that LLVM has special knowledge of are listed here. /// Additionally, this scheme allows LLVM to efficiently check for specific /// operand bundle tags without comparing strings. - enum { + enum : unsigned { OB_deopt = 0, // "deopt" OB_funclet = 1, // "funclet" OB_gc_transition = 2, // "gc-transition" diff --git a/llvm/lib/Target/AArch64/AArch64TargetTransformInfo.cpp b/llvm/lib/Target/AArch64/AArch64TargetTransformInfo.cpp index 1820ad959fc..aafcd7fe19f 100644 --- a/llvm/lib/Target/AArch64/AArch64TargetTransformInfo.cpp +++ b/llvm/lib/Target/AArch64/AArch64TargetTransformInfo.cpp @@ -277,7 +277,7 @@ int AArch64TTIImpl::getCastInstrCost(unsigned Opcode, Type *Dst, Type *Src, // same as the second operand. In this case, we will generate a "long" // version of the widening instruction. if (auto *Cast = dyn_cast<CastInst>(SingleUser->getOperand(1))) - if (I->getOpcode() == Cast->getOpcode() && + if (I->getOpcode() == unsigned(Cast->getOpcode()) && cast<CastInst>(I)->getSrcTy() == Cast->getSrcTy()) return 0; } diff --git a/llvm/lib/Target/ARM/AsmParser/ARMAsmParser.cpp b/llvm/lib/Target/ARM/AsmParser/ARMAsmParser.cpp index ff7376db878..55a73ff537c 100644 --- a/llvm/lib/Target/ARM/AsmParser/ARMAsmParser.cpp +++ b/llvm/lib/Target/ARM/AsmParser/ARMAsmParser.cpp @@ -6250,7 +6250,8 @@ bool ARMAsmParser::validateInstruction(MCInst &Inst, // The instruction must be predicable. if (!MCID.isPredicable()) return Error(Loc, "instructions in IT block must be predicable"); - unsigned Cond = Inst.getOperand(MCID.findFirstPredOperandIdx()).getImm(); + ARMCC::CondCodes Cond = ARMCC::CondCodes( + Inst.getOperand(MCID.findFirstPredOperandIdx()).getImm()); if (Cond != currentITCond()) { // Find the condition code Operand to get its SMLoc information. SMLoc CondLoc; @@ -6258,9 +6259,9 @@ bool ARMAsmParser::validateInstruction(MCInst &Inst, if (static_cast<ARMOperand &>(*Operands[I]).isCondCode()) CondLoc = Operands[I]->getStartLoc(); return Error(CondLoc, "incorrect condition in IT block; got '" + - StringRef(ARMCondCodeToString(ARMCC::CondCodes(Cond))) + - "', but expected '" + - ARMCondCodeToString(ARMCC::CondCodes(currentITCond())) + "'"); + StringRef(ARMCondCodeToString(Cond)) + + "', but expected '" + + ARMCondCodeToString(currentITCond()) + "'"); } // Check for non-'al' condition codes outside of the IT block. } else if (isThumbTwo() && MCID.isPredicable() && |
