diff options
| -rw-r--r-- | llvm/lib/Target/ARM/ARMAsmPrinter.cpp | 16 | ||||
| -rw-r--r-- | llvm/test/CodeGen/ARM/print-registers.ll | 10 |
2 files changed, 24 insertions, 2 deletions
diff --git a/llvm/lib/Target/ARM/ARMAsmPrinter.cpp b/llvm/lib/Target/ARM/ARMAsmPrinter.cpp index b227eaed8d6..a19584c7d40 100644 --- a/llvm/lib/Target/ARM/ARMAsmPrinter.cpp +++ b/llvm/lib/Target/ARM/ARMAsmPrinter.cpp @@ -367,6 +367,18 @@ bool ARMAsmPrinter::PrintAsmOperand(const MachineInstr *MI, unsigned OpNum, unsigned NumVals = InlineAsm::getNumOperandRegisters(Flags); unsigned RC; + bool FirstHalf; + const ARMBaseTargetMachine &ATM = + static_cast<const ARMBaseTargetMachine &>(TM); + + // 'Q' should correspond to the low order register and 'R' to the high + // order register. Whether this corresponds to the upper or lower half + // depends on the endianess mode. + if (ExtraCode[0] == 'Q') + FirstHalf = ATM.isLittleEndian(); + else + // ExtraCode[0] == 'R'. + FirstHalf = !ATM.isLittleEndian(); const TargetRegisterInfo *TRI = MF->getSubtarget().getRegisterInfo(); if (InlineAsm::hasRegClassConstraint(Flags, RC) && ARM::GPRPairRegClass.hasSubClassEq(TRI->getRegClass(RC))) { @@ -376,14 +388,14 @@ bool ARMAsmPrinter::PrintAsmOperand(const MachineInstr *MI, unsigned OpNum, if (!MO.isReg()) return true; const TargetRegisterInfo *TRI = MF->getSubtarget().getRegisterInfo(); - unsigned Reg = TRI->getSubReg(MO.getReg(), ExtraCode[0] == 'Q' ? + unsigned Reg = TRI->getSubReg(MO.getReg(), FirstHalf ? ARM::gsub_0 : ARM::gsub_1); O << ARMInstPrinter::getRegisterName(Reg); return false; } if (NumVals != 2) return true; - unsigned RegOp = ExtraCode[0] == 'Q' ? OpNum : OpNum + 1; + unsigned RegOp = FirstHalf ? OpNum : OpNum + 1; if (RegOp >= MI->getNumOperands()) return true; const MachineOperand &MO = MI->getOperand(RegOp); diff --git a/llvm/test/CodeGen/ARM/print-registers.ll b/llvm/test/CodeGen/ARM/print-registers.ll new file mode 100644 index 00000000000..a95a71db6d3 --- /dev/null +++ b/llvm/test/CodeGen/ARM/print-registers.ll @@ -0,0 +1,10 @@ +; RUN: llc -mtriple=armeb-arm-none-eabi < %s -o -| FileCheck %s -check-prefixes=CHECK-BE +; RUN: llc -mtriple=arm-arm-none-eabi < %s -o -| FileCheck %s -check-prefixes=CHECK-LE + +define dso_local void @_Z3fooi(i32 %a) local_unnamed_addr #0 { +entry: +; CHECK-BE: @ plain: [[LOW_REG:r[0-9]+]] Q: [[HIGH_REG:r[0-9]+]] R: [[LOW_REG]] H: [[HIGH_REG]] +; CHECK-LE: @ plain: [[LOW_REG:r[0-9]+]] Q: [[LOW_REG]] R: [[HIGH_REG:r[0-9]+]] H: [[HIGH_REG]] + tail call void asm sideeffect "// plain: $0 Q: ${0:Q} R: ${0:R} H: ${0:H}", "r"(i64 1) #1 + ret void +} |
