diff options
| -rw-r--r-- | llvm/lib/Target/AArch64/AArch64InstructionSelector.cpp | 3 | ||||
| -rw-r--r-- | llvm/test/CodeGen/AArch64/GlobalISel/select-implicit-def.mir | 30 |
2 files changed, 33 insertions, 0 deletions
diff --git a/llvm/lib/Target/AArch64/AArch64InstructionSelector.cpp b/llvm/lib/Target/AArch64/AArch64InstructionSelector.cpp index 5b387fb72d3..7e275e4d2f4 100644 --- a/llvm/lib/Target/AArch64/AArch64InstructionSelector.cpp +++ b/llvm/lib/Target/AArch64/AArch64InstructionSelector.cpp @@ -1325,6 +1325,9 @@ bool AArch64InstructionSelector::select(MachineInstr &I) const { case TargetOpcode::G_VASTART: return STI.isTargetDarwin() ? selectVaStartDarwin(I, MF, MRI) : selectVaStartAAPCS(I, MF, MRI); + case TargetOpcode::G_IMPLICIT_DEF: + I.setDesc(TII.get(TargetOpcode::IMPLICIT_DEF)); + return true; } return false; diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/select-implicit-def.mir b/llvm/test/CodeGen/AArch64/GlobalISel/select-implicit-def.mir new file mode 100644 index 00000000000..8604b2769ba --- /dev/null +++ b/llvm/test/CodeGen/AArch64/GlobalISel/select-implicit-def.mir @@ -0,0 +1,30 @@ +# RUN: llc -O0 -mtriple=aarch64-- -run-pass=instruction-select -verify-machineinstrs -global-isel %s -o - | FileCheck %s + +--- | + target datalayout = "e-m:o-i64:64-i128:128-n32:64-S128" + + define void @implicit_def() { ret void } +... + +--- +# CHECK-LABEL: name: implicit_def +name: implicit_def +legalized: true +regBankSelected: true +# CHECK: registers: +# CHECK-NEXT: - { id: 0, class: gpr32, preferred-register: '' } +# CHECK-NEXT: - { id: 1, class: gpr32, preferred-register: '' } +registers: + - { id: 0, class: gpr } + - { id: 1, class: gpr } + +# CHECK: body: +# CHECK: [[DEF:%[0-9]+]] = IMPLICIT_DEF +# CHECK: [[ADD:%[0-9]+]] = ADDWrr [[DEF]], [[DEF]] +# CHECK: %w0 = COPY [[ADD]] +body: | + bb.0: + %0(s32) = G_IMPLICIT_DEF + %1(s32) = G_ADD %0, %0 + %w0 = COPY %1(s32) +... |
