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-rwxr-xr-xpolly/include/polly/ScopInfo.h18
-rw-r--r--polly/lib/Analysis/ScopInfo.cpp23
-rw-r--r--polly/test/ScopInfo/loop_carry.ll10
-rw-r--r--polly/test/ScopInfo/multidim_ivs_and_integer_offsets_3d.ll2
-rw-r--r--polly/test/ScopInfo/multidim_ivs_and_parameteric_offsets_3d.ll2
-rw-r--r--polly/test/ScopInfo/multidim_only_ivs_2d.ll2
6 files changed, 39 insertions, 18 deletions
diff --git a/polly/include/polly/ScopInfo.h b/polly/include/polly/ScopInfo.h
index 50fd2b01cab..d7f608b5804 100755
--- a/polly/include/polly/ScopInfo.h
+++ b/polly/include/polly/ScopInfo.h
@@ -65,7 +65,6 @@ class MemoryAccess {
// DO NOT IMPLEMENT
const MemoryAccess &operator=(const MemoryAccess &);
-public:
/// @brief The access type of a memory access
///
/// There are three kind of access types:
@@ -75,24 +74,23 @@ public:
/// A certain set of memory locations are read and may be used for internal
/// calculations.
///
- /// * A write access
+ /// * A must-write access
///
/// A certain set of memory locactions is definitely written. The old value is
/// replaced by a newly calculated value. The old value is not read or used at
/// all.
///
- /// * A may write access
+ /// * A may-write access
///
/// A certain set of memory locactions may be written. The memory location may
/// contain a new value if there is actually a write or the old value may
/// remain, if no write happens.
enum AccessType {
Read,
- Write,
+ MustWrite,
MayWrite
};
-private:
isl_map *AccessRelation;
enum AccessType Type;
@@ -127,8 +125,16 @@ public:
/// @brief Is this a read memory access?
bool isRead() const { return Type == MemoryAccess::Read; }
+ /// @brief Is this a must-write memory access?
+ bool isMustWrite() const { return Type == MemoryAccess::MustWrite; }
+
+ /// @brief Is this a may-write memory access?
+ bool isMayWrite() const { return Type == MemoryAccess::MayWrite; }
+
/// @brief Is this a write memory access?
- bool isWrite() const { return Type == MemoryAccess::Write; }
+ bool isWrite() const {
+ return Type == MemoryAccess::MustWrite || Type == MemoryAccess::MayWrite;
+ }
isl_map *getAccessRelation() const;
diff --git a/polly/lib/Analysis/ScopInfo.cpp b/polly/lib/Analysis/ScopInfo.cpp
index 881375b34ad..56fcb72a37b 100644
--- a/polly/lib/Analysis/ScopInfo.cpp
+++ b/polly/lib/Analysis/ScopInfo.cpp
@@ -277,18 +277,23 @@ MemoryAccess::MemoryAccess(const IRAccess &Access, const Instruction *AccInst,
ScopStmt *Statement)
: Inst(AccInst) {
newAccessRelation = NULL;
- Type = Access.isRead() ? Read : Write;
statement = Statement;
BaseAddr = Access.getBase();
setBaseName();
if (!Access.isAffine()) {
- Type = (Type == Read) ? Read : MayWrite;
- AccessRelation = isl_map_from_basic_map(createBasicAccessMap(Statement));
+ // We overapproximate non-affine accesses with a possible access to the
+ // whole array. For read accesses it does not make a difference, if an
+ // access must or may happen. However, for write accesses it is important to
+ // differentiate between writes that must happen and writes that may happen.
+ AccessRelation = isl_map_from_basic_map(createBasicAccessMap(Statement));
+ Type = Access.isRead() ? Read : MayWrite;
return;
}
+ Type = Access.isRead() ? Read: MustWrite;
+
isl_pw_aff *Affine = SCEVAffinator::getPwAff(Statement, Access.getOffset());
// Divide the access function by the size of the elements in the array.
@@ -330,7 +335,17 @@ MemoryAccess::MemoryAccess(const Value *BaseAddress, ScopStmt *Statement) {
}
void MemoryAccess::print(raw_ostream &OS) const {
- OS.indent(12) << (isRead() ? "Read" : "Write") << "Access := \n";
+ switch (Type) {
+ case Read:
+ OS.indent(12) << "ReadAccess := \n";
+ break;
+ case MustWrite:
+ OS.indent(12) << "MustWriteAccess := \n";
+ break;
+ case MayWrite:
+ OS.indent(12) << "MayWriteAccess := \n";
+ break;
+ }
OS.indent(16) << getAccessRelationStr() << ";\n";
}
diff --git a/polly/test/ScopInfo/loop_carry.ll b/polly/test/ScopInfo/loop_carry.ll
index 7b69f571f36..35220f637ec 100644
--- a/polly/test/ScopInfo/loop_carry.ll
+++ b/polly/test/ScopInfo/loop_carry.ll
@@ -56,9 +56,9 @@ bb2: ; preds = %bb, %entry
; CHECK: [n] -> { Stmt_bb_nph[] -> scattering[0, 0, 0] };
; CHECK: ReadAccess :=
; CHECK: [n] -> { Stmt_bb_nph[] -> MemRef_a[0] };
-; CHECK: WriteAccess :=
+; CHECK: MustWriteAccess :=
; CHECK: [n] -> { Stmt_bb_nph[] -> MemRef_k_05_reg2mem[0] };
-; CHECK: WriteAccess :=
+; CHECK: MustWriteAccess :=
; CHECK: [n] -> { Stmt_bb_nph[] -> MemRef__reg2mem[0] };
; CHECK: Stmt_bb
; CHECK: Domain :=
@@ -69,13 +69,13 @@ bb2: ; preds = %bb, %entry
; CHECK: [n] -> { Stmt_bb[i0] -> MemRef__reg2mem[0] };
; CHECK: ReadAccess :=
; CHECK: [n] -> { Stmt_bb[i0] -> MemRef_k_05_reg2mem[0] };
-; CHECK: WriteAccess :=
+; CHECK: MustWriteAccess :=
; CHECK: [n] -> { Stmt_bb[i0] -> MemRef_a[1 + i0] };
; CHECK: ReadAccess :=
; CHECK: [n] -> { Stmt_bb[i0] -> MemRef_a[2 + 2i0] };
; CHECK: ReadAccess :=
; CHECK: [n] -> { Stmt_bb[i0] -> MemRef_a[4 + i0] };
-; CHECK: WriteAccess :=
+; CHECK: MustWriteAccess :=
; CHECK: [n] -> { Stmt_bb[i0] -> MemRef_k_05_reg2mem[0] };
-; CHECK: WriteAccess :=
+; CHECK: MustWriteAccess :=
; CHECK: [n] -> { Stmt_bb[i0] -> MemRef__reg2mem[0] };
diff --git a/polly/test/ScopInfo/multidim_ivs_and_integer_offsets_3d.ll b/polly/test/ScopInfo/multidim_ivs_and_integer_offsets_3d.ll
index 8a62f07e0f0..feaae8cf002 100644
--- a/polly/test/ScopInfo/multidim_ivs_and_integer_offsets_3d.ll
+++ b/polly/test/ScopInfo/multidim_ivs_and_integer_offsets_3d.ll
@@ -71,6 +71,6 @@ end:
; CHECK: [n, m, o] -> { Stmt_for_k[i0, i1, i2] : i0 >= 0 and i0 <= -1 + n and i1 >= 0 and i1 <= -1 + m and i2 >= 0 and i2 <= -1 + o };
; CHECK: Scattering
; CHECK: [n, m, o] -> { Stmt_for_k[i0, i1, i2] -> scattering[0, i0, 0, i1, 0, i2, 0] };
-; CHECK: WriteAccess
+; CHECK: MayWriteAccess
; CHECK: [n, m, o] -> { Stmt_for_k[i0, i1, i2] -> MemRef_A[o0] };
diff --git a/polly/test/ScopInfo/multidim_ivs_and_parameteric_offsets_3d.ll b/polly/test/ScopInfo/multidim_ivs_and_parameteric_offsets_3d.ll
index 228ee795477..635ba9b7fab 100644
--- a/polly/test/ScopInfo/multidim_ivs_and_parameteric_offsets_3d.ll
+++ b/polly/test/ScopInfo/multidim_ivs_and_parameteric_offsets_3d.ll
@@ -70,5 +70,5 @@ end:
; CHECK: [n, m, o] -> { Stmt_for_k[i0, i1, i2] : i0 >= 0 and i0 <= -1 + n and i1 >= 0 and i1 <= -1 + m and i2 >= 0 and i2 <= -1 + o };
; CHECK: Scattering
; CHECK: [n, m, o] -> { Stmt_for_k[i0, i1, i2] -> scattering[0, i0, 0, i1, 0, i2, 0] };
-; CHECK: WriteAccess
+; CHECK: MayWriteAccess
; CHECK: [n, m, o] -> { Stmt_for_k[i0, i1, i2] -> MemRef_A[o0] };
diff --git a/polly/test/ScopInfo/multidim_only_ivs_2d.ll b/polly/test/ScopInfo/multidim_only_ivs_2d.ll
index 7fe8e6e49a7..e99674292b2 100644
--- a/polly/test/ScopInfo/multidim_only_ivs_2d.ll
+++ b/polly/test/ScopInfo/multidim_only_ivs_2d.ll
@@ -50,6 +50,6 @@ end:
; CHECK: [n, m] -> { Stmt_for_j[i0, i1] : i0 >= 0 and i0 <= -1 + n and i1 >= 0 and i1 <= -1 + m };
; CHECK: Scattering :=
; CHECK: [n, m] -> { Stmt_for_j[i0, i1] -> scattering[0, i0, 0, i1, 0] };
-; CHECK: WriteAccess :=
+; CHECK: MayWriteAccess :=
; CHECK: [n, m] -> { Stmt_for_j[i0, i1] -> MemRef_A[o0] };
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