diff options
| -rw-r--r-- | llvm/lib/Target/AArch64/AArch64InstrInfo.cpp | 8 | ||||
| -rw-r--r-- | llvm/test/CodeGen/AArch64/neon-spill-fpr8-fpr16.ll | 30 |
2 files changed, 38 insertions, 0 deletions
diff --git a/llvm/lib/Target/AArch64/AArch64InstrInfo.cpp b/llvm/lib/Target/AArch64/AArch64InstrInfo.cpp index 9c27f82d2b3..092af05e199 100644 --- a/llvm/lib/Target/AArch64/AArch64InstrInfo.cpp +++ b/llvm/lib/Target/AArch64/AArch64InstrInfo.cpp @@ -487,6 +487,10 @@ AArch64InstrInfo::storeRegToStackSlot(MachineBasicBlock &MBB, default: llvm_unreachable("Unknown size for regclass"); } + } else if (AArch64::FPR8RegClass.hasSubClassEq(RC)) { + StoreOp = AArch64::LSFP8_STR; + } else if (AArch64::FPR16RegClass.hasSubClassEq(RC)) { + StoreOp = AArch64::LSFP16_STR; } else if (RC->hasType(MVT::f32) || RC->hasType(MVT::f64) || RC->hasType(MVT::f128)) { switch (RC->getSize()) { @@ -553,6 +557,10 @@ AArch64InstrInfo::loadRegFromStackSlot(MachineBasicBlock &MBB, default: llvm_unreachable("Unknown size for regclass"); } + } else if (AArch64::FPR8RegClass.hasSubClassEq(RC)) { + LoadOp = AArch64::LSFP8_LDR; + } else if (AArch64::FPR16RegClass.hasSubClassEq(RC)) { + LoadOp = AArch64::LSFP16_LDR; } else if (RC->hasType(MVT::f32) || RC->hasType(MVT::f64) || RC->hasType(MVT::f128)) { switch (RC->getSize()) { diff --git a/llvm/test/CodeGen/AArch64/neon-spill-fpr8-fpr16.ll b/llvm/test/CodeGen/AArch64/neon-spill-fpr8-fpr16.ll new file mode 100644 index 00000000000..bb3300ee9a9 --- /dev/null +++ b/llvm/test/CodeGen/AArch64/neon-spill-fpr8-fpr16.ll @@ -0,0 +1,30 @@ +; RUN: llc -mtriple=aarch64-none-linux-gnu -mattr=+neon < %s | FileCheck %s + +; This file tests the spill of FPR8/FPR16. The volatile loads/stores force the +; allocator to keep the value live until it's needed. + +%bigtype_v1i8 = type [20 x <1 x i8>] + +define void @spill_fpr8(%bigtype_v1i8* %addr) { +; CHECK-LABEL: spill_fpr8: +; CHECK: 1-byte Folded Spill +; CHECK: 1-byte Folded Reload + %val1 = load volatile %bigtype_v1i8* %addr + %val2 = load volatile %bigtype_v1i8* %addr + store volatile %bigtype_v1i8 %val1, %bigtype_v1i8* %addr + store volatile %bigtype_v1i8 %val2, %bigtype_v1i8* %addr + ret void +} + +%bigtype_v1i16 = type [20 x <1 x i16>] + +define void @spill_fpr16(%bigtype_v1i16* %addr) { +; CHECK-LABEL: spill_fpr16: +; CHECK: 2-byte Folded Spill +; CHECK: 2-byte Folded Reload + %val1 = load volatile %bigtype_v1i16* %addr + %val2 = load volatile %bigtype_v1i16* %addr + store volatile %bigtype_v1i16 %val1, %bigtype_v1i16* %addr + store volatile %bigtype_v1i16 %val2, %bigtype_v1i16* %addr + ret void +}
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