diff options
| -rw-r--r-- | llvm/test/CodeGen/X86/sse3-intrinsics-fast-isel.ll | 8 | ||||
| -rw-r--r-- | llvm/test/CodeGen/X86/sse4a-intrinsics-fast-isel.ll | 4 | ||||
| -rw-r--r-- | llvm/test/CodeGen/X86/ssse3-intrinsics-fast-isel.ll | 9 |
3 files changed, 11 insertions, 10 deletions
diff --git a/llvm/test/CodeGen/X86/sse3-intrinsics-fast-isel.ll b/llvm/test/CodeGen/X86/sse3-intrinsics-fast-isel.ll index 217be9aeae3..44e4a8c96a0 100644 --- a/llvm/test/CodeGen/X86/sse3-intrinsics-fast-isel.ll +++ b/llvm/test/CodeGen/X86/sse3-intrinsics-fast-isel.ll @@ -1,6 +1,6 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -; RUN: llc < %s -fast-isel -mtriple=i386-unknown-unknown -mattr=+sse3 | FileCheck %s --check-prefix=ALL --check-prefix=X32 -; RUN: llc < %s -fast-isel -mtriple=x86_64-unknown-unknown -mattr=+sse3 | FileCheck %s --check-prefix=ALL --check-prefix=X64 +; RUN: llc < %s -fast-isel -mtriple=i386-unknown-unknown -mattr=+sse3 | FileCheck %s --check-prefix=ALL --check-prefix=X32 +; RUN: llc < %s -fast-isel -mtriple=x86_64-unknown-unknown -mattr=+sse3 | FileCheck %s --check-prefix=ALL --check-prefix=X64 ; NOTE: This should use IR equivalent to what is generated by clang/test/CodeGen/sse3-builtins.c @@ -115,12 +115,12 @@ define <2 x double> @test_mm_loaddup_pd(double* %a0) { ; X32-LABEL: test_mm_loaddup_pd: ; X32: # BB#0: ; X32-NEXT: movl {{[0-9]+}}(%esp), %eax -; X32-NEXT: movddup (%eax), %xmm0 +; X32-NEXT: movddup {{.*#+}} xmm0 = mem[0,0] ; X32-NEXT: retl ; ; X64-LABEL: test_mm_loaddup_pd: ; X64: # BB#0: -; X64-NEXT: movddup (%rdi), %xmm0 +; X64-NEXT: movddup {{.*#+}} xmm0 = mem[0,0] ; X64-NEXT: retq %ld = load double, double* %a0 %res0 = insertelement <2 x double> undef, double %ld, i32 0 diff --git a/llvm/test/CodeGen/X86/sse4a-intrinsics-fast-isel.ll b/llvm/test/CodeGen/X86/sse4a-intrinsics-fast-isel.ll index f93a16a5eb3..777063ba6b8 100644 --- a/llvm/test/CodeGen/X86/sse4a-intrinsics-fast-isel.ll +++ b/llvm/test/CodeGen/X86/sse4a-intrinsics-fast-isel.ll @@ -1,6 +1,6 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -; RUN: llc < %s -fast-isel -mtriple=i386-unknown-unknown -mattr=+sse4a | FileCheck %s --check-prefix=ALL --check-prefix=X32 -; RUN: llc < %s -fast-isel -mtriple=x86_64-unknown-unknown -mattr=+sse4a | FileCheck %s --check-prefix=ALL --check-prefix=X64 +; RUN: llc < %s -fast-isel -mtriple=i386-unknown-unknown -mattr=+sse4a | FileCheck %s --check-prefix=ALL --check-prefix=X32 +; RUN: llc < %s -fast-isel -mtriple=x86_64-unknown-unknown -mattr=+sse4a | FileCheck %s --check-prefix=ALL --check-prefix=X64 ; NOTE: This should use IR equivalent to what is generated by clang/test/CodeGen/sse4a-builtins.c diff --git a/llvm/test/CodeGen/X86/ssse3-intrinsics-fast-isel.ll b/llvm/test/CodeGen/X86/ssse3-intrinsics-fast-isel.ll index 4f7ff20c6e0..352d45a4857 100644 --- a/llvm/test/CodeGen/X86/ssse3-intrinsics-fast-isel.ll +++ b/llvm/test/CodeGen/X86/ssse3-intrinsics-fast-isel.ll @@ -1,5 +1,6 @@ -; RUN: llc < %s -fast-isel -mtriple=i386-unknown-unknown -mattr=ssse3 | FileCheck %s --check-prefix=ALL --check-prefix=X32 -; RUN: llc < %s -fast-isel -mtriple=x86_64-unknown-unknown -mattr=ssse3 | FileCheck %s --check-prefix=ALL --check-prefix=X64 +; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py +; RUN: llc < %s -fast-isel -mtriple=i386-unknown-unknown -mattr=ssse3 | FileCheck %s --check-prefix=ALL --check-prefix=X32 +; RUN: llc < %s -fast-isel -mtriple=x86_64-unknown-unknown -mattr=ssse3 | FileCheck %s --check-prefix=ALL --check-prefix=X64 ; NOTE: This should use IR equivalent to what is generated by clang/test/CodeGen/ssse3-builtins.c @@ -57,13 +58,13 @@ declare <4 x i32> @llvm.x86.ssse3.pabs.d.128(<4 x i32>) nounwind readnone define <2 x i64> @test_mm_alignr_epi8(<2 x i64> %a0, <2 x i64> %a1) { ; X32-LABEL: test_mm_alignr_epi8: ; X32: # BB#0: -; X32-NEXT: palignr {{.*#}} xmm1 = xmm0[2,3,4,5,6,7,8,9,10,11,12,13,14,15],xmm1[0,1] +; X32-NEXT: palignr {{.*#+}} xmm1 = xmm0[2,3,4,5,6,7,8,9,10,11,12,13,14,15],xmm1[0,1] ; X32-NEXT: movdqa %xmm1, %xmm0 ; X32-NEXT: retl ; ; X64-LABEL: test_mm_alignr_epi8: ; X64: # BB#0: -; X64-NEXT: palignr {{.*#}} xmm1 = xmm0[2,3,4,5,6,7,8,9,10,11,12,13,14,15],xmm1[0,1] +; X64-NEXT: palignr {{.*#+}} xmm1 = xmm0[2,3,4,5,6,7,8,9,10,11,12,13,14,15],xmm1[0,1] ; X64-NEXT: movdqa %xmm1, %xmm0 ; X64-NEXT: retq %arg0 = bitcast <2 x i64> %a0 to <16 x i8> |
